```python
import torch
import torch.nn as nn
from torch.utils.cpp_extension import load_inline


_cpp_source = r"""
#include <torch/extension.h>

torch::Tensor tiled_conv1d_cuda(
    torch::Tensor x,
    torch::Tensor weight,
    c10::optional<torch::Tensor> bias,
    int64_t stride,
    int64_t padding,
    int64_t dilation,
    int64_t groups);
"""

_cuda_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <c10/cuda/CUDAException.h>
#include <cuda_runtime.h>

template <bool Fast>
__global__ void conv1d_kernel(
    const float* __restrict__ x,
    const float* __restrict__ weight,
    const float* __restrict__ bias,
    float* __restrict__ output,
    int64_t length,
    int64_t output_length,
    int64_t input_channels,
    int64_t output_channels,
    int64_t channels_per_group,
    int64_t outputs_per_group,
    int64_t kernel_size,
    int64_t stride,
    int64_t padding,
    int64_t dilation,
    int64_t tiles_per_group)
{
    constexpr int BM = 64;
    constexpr int BN = 128;
    constexpr int BK = 32;

    __shared__ float weights_tile[BM][BK + 1];
    __shared__ float input_tile[BK][BN];

    const int tid = threadIdx.x;
    const int column_lane = tid & 15;
    const int row_lane = tid >> 4;

    const int64_t group = blockIdx.y / tiles_per_group;
    const int64_t output_base =
        (blockIdx.y % tiles_per_group) * BM;
    const int64_t position_base = int64_t(blockIdx.x) * BN;
    const int64_t batch = blockIdx.z;

    const int64_t ks = Fast ? 3 : kernel_size;
    const int64_t reduction_size = channels_per_group * ks;
    const int64_t global_output_base =
        group * outputs_per_group + output_base;

    const float* input_batch =
        x + (batch * input_channels + group * channels_per_group) * length;

    float accum[4][8];

    #pragma unroll
    for (int i = 0; i < 4; ++i) {
        #pragma unroll
        for (int j = 0; j < 8; ++j) {
            accum[i][j] = 0.0f;
        }
    }

    for (int64_t reduction_base = 0;
         reduction_base < reduction_size;
         reduction_base += BK) {

        #pragma unroll
        for (int index = tid; index < BM * BK; index += 256) {
            const int row = index / BK;
            const int k = index % BK;
            const int64_t reduction = reduction_base + k;
            float value = 0.0f;

            if (output_base + row < outputs_per_group &&
                reduction < reduction_size) {
                value = weight[
                    (global_output_base + row) * reduction_size + reduction];
            }
            weights_tile[row][k] = value;
        }

        #pragma unroll
        for (int index = tid; index < BK * BN; index += 256) {
            const int k = index / BN;
            const int column = index % BN;
            const int64_t reduction = reduction_base + k;
            const int64_t channel = reduction / ks;
            const int64_t tap = reduction % ks;
            const int64_t out_position = position_base + column;

            const int64_t input_position = Fast
                ? out_position + tap
                : out_position * stride - padding + tap * dilation;

            float value = 0.0f;
            if (reduction < reduction_size &&
                out_position < output_length &&
                input_position >= 0 &&
                input_position < length) {
                value = input_batch[channel * length + input_position];
            }
            input_tile[k][column] = value;
        }

        __syncthreads();

        #pragma unroll
        for (int k = 0; k < BK; ++k) {
            float a[4];

            #pragma unroll
            for (int i = 0; i < 4; ++i) {
                a[i] = weights_tile[row_lane + i * 16][k];
            }

            #pragma unroll
            for (int j = 0; j < 8; ++j) {
                const float b = input_tile[k][column_lane + j * 16];

                #pragma unroll
                for (int i = 0; i < 4; ++i) {
                    accum[i][j] = fmaf(a[i], b, accum[i][j]);
                }
            }
        }

        __syncthreads();
    }

    #pragma unroll
    for (int i = 0; i < 4; ++i) {
        const int64_t local_channel = output_base + row_lane + i * 16;
        const int64_t channel =
            group * outputs_per_group + local_channel;

        if (local_channel < outputs_per_group) {
            const float bias_value = bias ? bias[channel] : 0.0f;

            #pragma unroll
            for (int j = 0; j < 8; ++j) {
                const int64_t position =
                    position_base + column_lane + j * 16;

                if (position < output_length) {
                    output[
                        (batch * output_channels + channel) * output_length
                        + position
                    ] = accum[i][j] + bias_value;
                }
            }
        }
    }
}

torch::Tensor tiled_conv1d_cuda(
    torch::Tensor x,
    torch::Tensor weight,
    c10::optional<torch::Tensor> bias,
    int64_t stride,
    int64_t padding,
    int64_t dilation,
    int64_t groups)
{
    TORCH_CHECK(x.is_cuda() && weight.is_cuda(), "Expected CUDA tensors");
    TORCH_CHECK(x.scalar_type() == at::kFloat &&
                weight.scalar_type() == at::kFloat, "Expected float32 tensors");
    TORCH_CHECK(x.dim() == 3 && weight.dim() == 3, "Expected 3D tensors");
    TORCH_CHECK(x.is_contiguous() && weight.is_contiguous(),
                "Expected contiguous tensors");
    TORCH_CHECK(x.device() == weight.device(), "Device mismatch");
    TORCH_CHECK(groups > 0 && stride > 0 && dilation > 0 && padding >= 0,
                "Invalid convolution parameters");

    const c10::cuda::CUDAGuard device_guard(x.device());

    const int64_t batch = x.size(0);
    const int64_t input_channels = x.size(1);
    const int64_t length = x.size(2);
    const int64_t output_channels = weight.size(0);
    const int64_t channels_per_group = weight.size(1);
    const int64_t kernel_size = weight.size(2);

    TORCH_CHECK(input_channels == channels_per_group * groups &&
                output_channels % groups == 0,
                "Invalid grouped convolution dimensions");
    TORCH_CHECK(kernel_size > 0 && channels_per_group > 0 &&
                output_channels > 0, "Invalid convolution shape");

    const int64_t numerator =
        length + 2 * padding - dilation * (kernel_size - 1) - 1;
    TORCH_CHECK(numerator >= 0, "Kernel exceeds padded input length");

    const int64_t output_length = numerator / stride + 1;
    const int64_t outputs_per_group = output_channels / groups;
    const int64_t tiles_per_group = (outputs_per_group + 63) / 64;

    const float* bias_ptr = nullptr;
    if (bias.has_value()) {
        const auto& b = bias.value();
        TORCH_CHECK(b.is_cuda() && b.device() == x.device() &&
                    b.scalar_type() == at::kFloat && b.is_contiguous() &&
                    b.dim() == 1 && b.numel() == output_channels,
                    "Invalid bias");
        bias_ptr = b.data_ptr<float>();
    }

    auto output =
        torch::empty({batch, output_channels, output_length}, x.options());

    if (batch == 0) {
        return output;
    }

    TORCH_CHECK(batch <= 65535 && tiles_per_group * groups <= 65535,
                "Convolution exceeds CUDA grid limits");

    const dim3 grid(
        static_cast<unsigned int>((output_length + 127) / 128),
        static_cast<unsigned int>(tiles_per_group * groups),
        static_cast<unsigned int>(batch));
    const auto stream = at::cuda::getCurrentCUDAStream();

    if (kernel_size == 3 && stride == 1 && padding == 0 && dilation == 1) {
        conv1d_kernel<true><<<grid, 256, 0, stream>>>(
            x.data_ptr<float>(), weight.data_ptr<float>(), bias_ptr,
            output.data_ptr<float>(), length, output_length,
            input_channels, output_channels, channels_per_group,
            outputs_per_group, kernel_size, stride, padding, dilation,
            tiles_per_group);
    } else {
        conv1d_kernel<false><<<grid, 256, 0, stream>>>(
            x.data_ptr<float>(), weight.data_ptr<float>(), bias_ptr,
            output.data_ptr<float>(), length, output_length,
            input_channels, output_channels, channels_per_group,
            outputs_per_group, kernel_size, stride, padding, dilation,
            tiles_per_group);
    }

    C10_CUDA_KERNEL_LAUNCH_CHECK();
    return output;
}
"""

_extension = None


def _get_extension():
    global _extension
    if _extension is None:
        _extension = load_inline(
            name="tiled_fp32_conv1d_ext",
            cpp_sources=_cpp_source,
            cuda_sources=_cuda_source,
            functions=["tiled_conv1d_cuda"],
            extra_cflags=["-O3"],
            extra_cuda_cflags=["-O3"],
            verbose=False,
        )
    return _extension


class _Conv1dFunction(torch.autograd.Function):
    @staticmethod
    def forward(ctx, x, weight, bias, stride, padding, dilation, groups):
        ctx.save_for_backward(x, weight)
        ctx.parameters = (stride, padding, dilation, groups)
        ctx.has_bias = bias is not None
        return _get_extension().tiled_conv1d_cuda(
            x, weight, bias, stride, padding, dilation, groups
        )

    @staticmethod
    def backward(ctx, grad_output):
        x, weight = ctx.saved_tensors
        stride, padding, dilation, groups = ctx.parameters
        grad_x = grad_weight = grad_bias = None

        if ctx.needs_input_grad[0]:
            grad_x = torch.nn.grad.conv1d_input(
                x.shape, weight, grad_output,
                stride, padding, dilation, groups,
            )
        if ctx.needs_input_grad[1]:
            grad_weight = torch.nn.grad.conv1d_weight(
                x, weight.shape, grad_output,
                stride, padding, dilation, groups,
            )
        if ctx.has_bias and ctx.needs_input_grad[2]:
            grad_bias = grad_output.sum(dim=(0, 2))

        return grad_x, grad_weight, grad_bias, None, None, None, None


class ModelNew(nn.Module):
    def __init__(
        self,
        in_channels: int,
        out_channels: int,
        kernel_size: int,
        stride: int = 1,
        padding: int = 0,
        dilation: int = 1,
        groups: int = 1,
        bias: bool = False,
    ):
        super().__init__()
        self.conv1d = nn.Conv1d(
            in_channels,
            out_channels,
            kernel_size,
            stride=stride,
            padding=padding,
            dilation=dilation,
            groups=groups,
            bias=bias,
        )

    def forward(self, x: torch.Tensor) -> torch.Tensor:
        conv = self.conv1d
        if (
            not x.is_cuda
            or x.dtype != torch.float32
            or conv.weight.dtype != torch.float32
            or x.ndim != 3
            or isinstance(conv.padding, str)
            or torch.is_autocast_enabled()
            or x.shape[0] > 65535
            or ((conv.out_channels // conv.groups + 63) // 64)
               * conv.groups > 65535
        ):
            return conv(x)

        return _Conv1dFunction.apply(
            x.contiguous(),
            conv.weight.contiguous(),
            conv.bias,
            conv.stride[0],
            conv.padding[0],
            conv.dilation[0],
            conv.groups,
        )
```