```python
import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline


_cpp_source = r"""
#include <torch/extension.h>

torch::Tensor to_channels_last_cuda(torch::Tensor x);
torch::Tensor fused_activation_cuda(
    torch::Tensor x, torch::Tensor bias, double add_value, double scale);
"""

_cuda_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <c10/cuda/CUDAException.h>
#include <cuda_runtime.h>
#include <algorithm>
#include <cstdint>

__global__ void transpose_layout_kernel(
    const float* __restrict__ input,
    float* __restrict__ output,
    int channels,
    int64_t spatial) {

    __shared__ float tile[32][33];

    const int tx = threadIdx.x;
    const int ty = threadIdx.y;
    const int channel_base = blockIdx.y * 32;
    const int64_t spatial_base = int64_t(blockIdx.x) * 32;
    const int64_t batch_base = int64_t(blockIdx.z) * channels * spatial;

    #pragma unroll
    for (int j = 0; j < 32; j += 8) {
        const int c = channel_base + ty + j;
        const int64_t s = spatial_base + tx;
        if (c < channels && s < spatial) {
            tile[ty + j][tx] = input[batch_base + int64_t(c) * spatial + s];
        }
    }

    __syncthreads();

    #pragma unroll
    for (int j = 0; j < 32; j += 8) {
        const int c = channel_base + tx;
        const int64_t s = spatial_base + ty + j;
        if (c < channels && s < spatial) {
            output[batch_base + s * channels + c] = tile[tx][ty + j];
        }
    }
}

torch::Tensor to_channels_last_cuda(torch::Tensor x) {
    TORCH_CHECK(x.is_cuda() && x.scalar_type() == at::kFloat,
                "Expected a CUDA float32 tensor");
    TORCH_CHECK(x.dim() == 4, "Expected a four-dimensional tensor");

    if (x.is_contiguous(at::MemoryFormat::ChannelsLast)) {
        return x;
    }

    const c10::cuda::CUDAGuard guard(x.device());
    const int64_t spatial = x.size(2) * x.size(3);

    if (!x.is_contiguous() ||
        x.size(0) > 65535 ||
        x.size(1) > 65535LL * 32 ||
        spatial > 2147483647LL * 32) {
        return x.contiguous(at::MemoryFormat::ChannelsLast);
    }

    auto output = torch::empty(
        {x.size(0), x.size(2), x.size(3), x.size(1)},
        x.options()).permute({0, 3, 1, 2});

    if (x.numel() == 0) {
        return output;
    }

    const dim3 block(32, 8);
    const dim3 grid(
        static_cast<unsigned int>((spatial + 31) / 32),
        static_cast<unsigned int>((x.size(1) + 31) / 32),
        static_cast<unsigned int>(x.size(0)));

    transpose_layout_kernel<<<grid, block, 0,
        at::cuda::getCurrentCUDAStream()>>>(
        x.data_ptr<float>(),
        output.data_ptr<float>(),
        static_cast<int>(x.size(1)),
        spatial);

    C10_CUDA_KERNEL_LAUNCH_CHECK();
    return output;
}

__device__ __forceinline__ float activate(
    float value, float bias, float add_value, float scale) {

    const float x = __fadd_rn(value, bias);
    const float e = __expf(fminf(x, 20.0f));
    const float numerator = e * (e + 2.0f);
    const float gate = __fdividef(numerator, numerator + 2.0f);
    float y = __fadd_rn(__fmul_rn(x, gate), add_value);
    y = y < -1.0f ? -1.0f : y;
    y = y > 1.0f ? 1.0f : y;
    return __fmul_rn(y, scale);
}

__device__ __forceinline__ float4 activate4(
    float4 value, float4 bias, float add_value, float scale) {

    return make_float4(
        activate(value.x, bias.x, add_value, scale),
        activate(value.y, bias.y, add_value, scale),
        activate(value.z, bias.z, add_value, scale),
        activate(value.w, bias.w, add_value, scale));
}

template<bool Channels64>
__global__ void fused_vector_kernel(
    float4* __restrict__ data,
    const float4* __restrict__ bias,
    int64_t count,
    int channels4,
    float add_value,
    float scale) {

    constexpr int threads = 256;
    const int64_t first =
        int64_t(blockIdx.x) * (threads * 2) + threadIdx.x;
    const int64_t step = int64_t(gridDim.x) * (threads * 2);

    float4 fixed_bias;
    if (Channels64) {
        fixed_bias = bias[threadIdx.x & 15];
    }

    for (int64_t i = first; i < count; i += step) {
        const bool second_valid = i + threads < count;
        const float4 v0 = data[i];
        float4 v1;
        if (second_valid) {
            v1 = data[i + threads];
        }

        const float4 b0 =
            Channels64 ? fixed_bias : bias[i % channels4];
        const float4 result0 = activate4(v0, b0, add_value, scale);

        if (second_valid) {
            const float4 b1 = Channels64
                ? fixed_bias
                : bias[(i + threads) % channels4];
            const float4 result1 = activate4(v1, b1, add_value, scale);
            data[i] = result0;
            data[i + threads] = result1;
        } else {
            data[i] = result0;
        }
    }
}

__global__ void fused_scalar_kernel(
    float* __restrict__ data,
    const float* __restrict__ bias,
    int64_t count,
    int channels,
    float add_value,
    float scale) {

    const int64_t first = int64_t(blockIdx.x) * blockDim.x + threadIdx.x;
    const int64_t step = int64_t(gridDim.x) * blockDim.x;

    for (int64_t i = first; i < count; i += step) {
        data[i] = activate(data[i], bias[i % channels], add_value, scale);
    }
}

torch::Tensor fused_activation_cuda(
    torch::Tensor x,
    torch::Tensor bias,
    double add_value,
    double scale) {

    TORCH_CHECK(x.is_cuda() && bias.is_cuda(),
                "Expected CUDA tensors");
    TORCH_CHECK(x.device() == bias.device(), "Device mismatch");
    TORCH_CHECK(x.scalar_type() == at::kFloat &&
                bias.scalar_type() == at::kFloat,
                "Expected float32 tensors");
    TORCH_CHECK(x.dim() == 4 &&
                x.is_contiguous(at::MemoryFormat::ChannelsLast),
                "Expected channels-last input");
    TORCH_CHECK(bias.is_contiguous() && bias.numel() == x.size(1),
                "Invalid bias");

    const c10::cuda::CUDAGuard guard(x.device());
    const int64_t count = x.numel();
    if (count == 0) {
        return x;
    }

    const int channels = static_cast<int>(x.size(1));
    const bool vectorized =
        channels % 4 == 0 &&
        reinterpret_cast<uintptr_t>(x.data_ptr<float>()) % 16 == 0 &&
        reinterpret_cast<uintptr_t>(bias.data_ptr<float>()) % 16 == 0;

    constexpr int threads = 256;
    const auto stream = at::cuda::getCurrentCUDAStream();
    const float add = static_cast<float>(add_value);
    const float mul = static_cast<float>(scale);

    if (vectorized) {
        const int64_t vectors = count / 4;
        const int blocks = static_cast<int>(
            std::min<int64_t>((vectors + 511) / 512, 4096));

        auto* data = reinterpret_cast<float4*>(x.data_ptr<float>());
        const auto* b =
            reinterpret_cast<const float4*>(bias.data_ptr<float>());

        if (channels == 64) {
            fused_vector_kernel<true><<<blocks, threads, 0, stream>>>(
                data, b, vectors, channels / 4, add, mul);
        } else {
            fused_vector_kernel<false><<<blocks, threads, 0, stream>>>(
                data, b, vectors, channels / 4, add, mul);
        }
    } else {
        const int blocks = static_cast<int>(
            std::min<int64_t>((count + threads - 1) / threads, 4096));

        fused_scalar_kernel<<<blocks, threads, 0, stream>>>(
            x.data_ptr<float>(), bias.data_ptr<float>(),
            count, channels, add, mul);
    }

    C10_CUDA_KERNEL_LAUNCH_CHECK();
    return x;
}
"""

_ops = load_inline(
    name="channels_last_fused_mish_scale_v6",
    cpp_sources=_cpp_source,
    cuda_sources=_cuda_source,
    functions=["to_channels_last_cuda", "fused_activation_cuda"],
    extra_cflags=["-O3"],
    extra_cuda_cflags=["-O3", "--fmad=false"],
    verbose=False,
)


class ModelNew(nn.Module):
    def __init__(
        self,
        in_channels,
        out_channels,
        kernel_size,
        stride,
        padding,
        output_padding,
        add_value,
        scale,
    ):
        super().__init__()
        self.conv_transpose = nn.ConvTranspose2d(
            in_channels,
            out_channels,
            kernel_size,
            stride,
            padding,
            output_padding,
        )
        self.conv_transpose.to(memory_format=torch.channels_last)
        self.add_value = add_value
        self.scale = scale

    def forward(self, x):
        conv = self.conv_transpose
        if (
            x.is_cuda
            and x.dtype == torch.float32
            and conv.weight.dtype == torch.float32
            and conv.bias is not None
            and conv.bias.dtype == torch.float32
            and not torch.is_autocast_enabled()
        ):
            x = _ops.to_channels_last_cuda(x)
            x = F.conv_transpose2d(
                x,
                conv.weight,
                bias=None,
                stride=conv.stride,
                padding=conv.padding,
                output_padding=conv.output_padding,
                groups=conv.groups,
                dilation=conv.dilation,
            )
            x = x.contiguous(memory_format=torch.channels_last)
            return _ops.fused_activation_cuda(
                x, conv.bias, float(self.add_value), float(self.scale)
            )

        return F.hardtanh(
            F.mish(conv(x)) + self.add_value,
            min_val=-1.0,
            max_val=1.0,
        ) * self.scale
```