You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Simple model that performs a matrix multiplication, adds a value, applies Swish, Tanh, GELU, and Hardtanh activation functions.
    """
    def __init__(self, in_features, out_features, add_value_shape):
        super(Model, self).__init__()
        self.matmul = nn.Linear(in_features, out_features)
        self.add_value = nn.Parameter(torch.randn(add_value_shape)) 

    def forward(self, x):
        x = self.matmul(x)
        x = x + self.add_value
        x = torch.sigmoid(x) * x # Swish
        x = torch.tanh(x)
        x = torch.nn.functional.gelu(x) # GELU
        x = torch.nn.functional.hardtanh(x, min_val=-1, max_val=1) # Hardtanh
        return x

batch_size = 1024
in_features = 8192
out_features = 8192
add_value_shape = (out_features,)

def get_inputs():
    return [torch.rand(batch_size, in_features)]

def get_init_inputs():
    return [in_features, out_features, add_value_shape]
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 5 of 6 for this task. Your previous solution (turn 4) was:
```python
import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

_cpp_source = r"""
#include <torch/extension.h>
torch::Tensor fused_linear_cuda(
    torch::Tensor x, torch::Tensor weight,
    torch::Tensor bias, torch::Tensor add);
"""

_cuda_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <c10/cuda/CUDAException.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cublas_v2.h>
#include <cublasLt.h>
#include <algorithm>
#include <cstdint>
#include <climits>
#include <memory>
#include <tuple>
#include <map>

constexpr size_t WORKSPACE_BYTES = 32ull * 1024 * 1024;

__device__ __forceinline__ unsigned int pack_half2(float a, float b) {
    const __half2_raw h = __floats2half2_rn(a, b);
    return static_cast<unsigned int>(h.x) |
           (static_cast<unsigned int>(h.y) << 16);
}

__global__ void pack4_kernel(
    const float4* __restrict__ weight,
    const float4* __restrict__ x,
    uint2* __restrict__ packed,
    int64_t weight_vectors,
    int64_t total_vectors
) {
    for (int64_t i = int64_t(blockIdx.x) * blockDim.x + threadIdx.x;
         i < total_vectors;
         i += int64_t(blockDim.x) * gridDim.x) {
        const float4 v =
            i < weight_vectors ? weight[i] : x[i - weight_vectors];
        const uint2 h = make_uint2(
            pack_half2(v.x, v.y), pack_half2(v.z, v.w));
        packed[i] = h;
    }
}

__global__ void pack_scalar_kernel(
    const float* __restrict__ weight,
    const float* __restrict__ x,
    half* __restrict__ packed,
    int64_t weight_count,
    int64_t total_count
) {
    for (int64_t i = int64_t(blockIdx.x) * blockDim.x + threadIdx.x;
         i < total_count;
         i += int64_t(blockDim.x) * gridDim.x) {
        packed[i] = __float2half_rn(
            i < weight_count ? weight[i] : x[i - weight_count]);
    }
}

__device__ __forceinline__ float activate(float x, float b, float a) {
    x = __fadd_rn(x, b);
    x = __fadd_rn(x, a);
    x = x / (1.0f + __expf(-x));
    x = tanhf(x);
    x = (0.5f * x) * (1.0f + erff(x * 0.7071067811865475f));
    return fminf(1.0f, fmaxf(-1.0f, x));
}

__global__ void activate4_kernel(
    float4* __restrict__ output,
    const float4* __restrict__ bias,
    const float4* __restrict__ add,
    int64_t count,
    int columns
) {
    for (int64_t i = int64_t(blockIdx.x) * blockDim.x + threadIdx.x;
         i < count;
         i += int64_t(blockDim.x) * gridDim.x) {
        const int col = i % columns;
        const float4 b = bias[col];
        const float4 a = add[col];
        float4 v = output[i];
        v.x = activate(v.x, b.x, a.x);
        v.y = activate(v.y, b.y, a.y);
        v.z = activate(v.z, b.z, a.z);
        v.w = activate(v.w, b.w, a.w);
        output[i] = v;
    }
}

__global__ void activate_scalar_kernel(
    float* __restrict__ output,
    const float* __restrict__ bias,
    const float* __restrict__ add,
    int64_t count,
    int columns
) {
    for (int64_t i = int64_t(blockIdx.x) * blockDim.x + threadIdx.x;
         i < count;
         i += int64_t(blockDim.x) * gridDim.x) {
        const int col = i % columns;
        output[i] = activate(output[i], bias[col], add[col]);
    }
}

static void check_blas(cublasStatus_t status) {
    TORCH_CHECK(status == CUBLAS_STATUS_SUCCESS,
                "cuBLAS error: ", static_cast<int>(status));
}

struct MatmulPlan {
    cublasLtHandle_t handle = nullptr;
    cublasLtMatmulDesc_t operation = nullptr;
    cublasLtMatrixLayout_t a = nullptr;
    cublasLtMatrixLayout_t b = nullptr;
    cublasLtMatrixLayout_t c = nullptr;
    cublasLtMatmulAlgo_t algorithm{};
    size_t workspace_size = 0;
    bool available = false;

    MatmulPlan(int m, int n, int k) {
        check_blas(cublasLtCreate(&handle));
        check_blas(cublasLtMatmulDescCreate(
            &operation, CUBLAS_COMPUTE_32F, CUDA_R_32F));

        cublasOperation_t transpose = CUBLAS_OP_T;
        cublasOperation_t normal = CUBLAS_OP_N;
        check_blas(cublasLtMatmulDescSetAttribute(
            operation, CUBLASLT_MATMUL_DESC_TRANSA,
            &transpose, sizeof(transpose)));
        check_blas(cublasLtMatmulDescSetAttribute(
            operation, CUBLASLT_MATMUL_DESC_TRANSB,
            &normal, sizeof(normal)));

        check_blas(cublasLtMatrixLayoutCreate(&a, CUDA_R_16F, k, n, k));
        check_blas(cublasLtMatrixLayoutCreate(&b, CUDA_R_16F, k, m, k));
        check_blas(cublasLtMatrixLayoutCreate(&c, CUDA_R_32F, n, m, n));

        cublasLtMatmulPreference_t preference = nullptr;
        check_blas(cublasLtMatmulPreferenceCreate(&preference));
        size_t maximum_workspace = WORKSPACE_BYTES;
        check_blas(cublasLtMatmulPreferenceSetAttribute(
            preference, CUBLASLT_MATMUL_PREF_MAX_WORKSPACE_BYTES,
            &maximum_workspace, sizeof(maximum_workspace)));

        // The second packed matrix starts immediately after the first.
        uint32_t alignment_a = 256;
        uint32_t alignment_b = 256;
        const uint64_t offset = uint64_t(n) * k * sizeof(half);
        while (alignment_b > 2 && offset % alignment_b != 0)
            alignment_b >>= 1;
        uint32_t alignment_c = 256;

        check_blas(cublasLtMatmulPreferenceSetAttribute(
            preference, CUBLASLT_MATMUL_PREF_MIN_ALIGNMENT_A_BYTES,
            &alignment_a, sizeof(alignment_a)));
        check_blas(cublasLtMatmulPreferenceSetAttribute(
            preference, CUBLASLT_MATMUL_PREF_MIN_ALIGNMENT_B_BYTES,
            &alignment_b, sizeof(alignment_b)));
        check_blas(cublasLtMatmulPreferenceSetAttribute(
            preference, CUBLASLT_MATMUL_PREF_MIN_ALIGNMENT_C_BYTES,
            &alignment_c, sizeof(alignment_c)));
        check_blas(cublasLtMatmulPreferenceSetAttribute(
            preference, CUBLASLT_MATMUL_PREF_MIN_ALIGNMENT_D_BYTES,
            &alignment_c, sizeof(alignment_c)));

        cublasLtMatmulHeuristicResult_t result{};
        int returned = 0;
        const auto status = cublasLtMatmulAlgoGetHeuristic(
            handle, operation, a, b, c, c, preference,
            1, &result, &returned);
        cublasLtMatmulPreferenceDestroy(preference);

        if (status == CUBLAS_STATUS_SUCCESS &&
            returned > 0 && result.state == CUBLAS_STATUS_SUCCESS) {
            algorithm = result.algo;
            workspace_size = result.workspaceSize;
            available = true;
        }
    }

    ~MatmulPlan() {
        if (a) cublasLtMatrixLayoutDestroy(a);
        if (b) cublasLtMatrixLayoutDestroy(b);
        if (c) cublasLtMatrixLayoutDestroy(c);
        if (operation) cublasLtMatmulDescDestroy(operation);
        if (handle) cublasLtDestroy(handle);
    }
};

static MatmulPlan& get_plan(int device, int m, int n, int k) {
    using Key = std::tuple<int, int, int, int>;
    static thread_local std::map<Key, std::unique_ptr<MatmulPlan>> plans;
    const Key key(device, m, n, k);
    auto it = plans.find(key);
    if (it == plans.end()) {
        it = plans.emplace(
            key, std::make_unique<MatmulPlan>(m, n, k)).first;
    }
    return *it->second;
}

static int blocks_for(int64_t count) {
    return static_cast<int>(
        std::min<int64_t>((count + 255) / 256, 4096));
}

torch::Tensor fused_linear_cuda(
    torch::Tensor x,
    torch::Tensor weight,
    torch::Tensor bias,
    torch::Tensor add
) {
    TORCH_CHECK(x.is_cuda() && weight.is_cuda() &&
                bias.is_cuda() && add.is_cuda(), "Expected CUDA tensors");
    TORCH_CHECK(x.device() == weight.device() &&
                x.device() == bias.device() &&
                x.device() == add.device(), "Device mismatch");
    TORCH_CHECK(x.scalar_type() == at::kFloat &&
                weight.scalar_type() == at::kFloat &&
                bias.scalar_type() == at::kFloat &&
                add.scalar_type() == at::kFloat, "Expected float32 tensors");
    TORCH_CHECK(x.is_contiguous() && weight.is_contiguous() &&
                bias.is_contiguous() && add.is_contiguous(),
                "Expected contiguous tensors");
    TORCH_CHECK(x.dim() == 2 && weight.dim() == 2 &&
                x.size(1) == weight.size(1), "Invalid matrix dimensions");
    TORCH_CHECK(bias.numel() == weight.size(0) &&
                add.numel() == weight.size(0), "Invalid bias dimensions");
    TORCH_CHECK(x.size(0) <= INT_MAX && weight.size(0) <= INT_MAX &&
                x.size(1) > 0 && x.size(1) <= INT_MAX,
                "Unsupported matrix dimensions");

    const c10::cuda::CUDAGuard guard(x.device());
    const int m = static_cast<int>(x.size(0));
    const int n = static_cast<int>(weight.size(0));
    const int k = static_cast<int>(x.size(1));
    auto output = torch::empty({m, n}, x.options());
    if (m == 0 || n == 0) return output;

    const cudaStream_t stream = at::cuda::getCurrentCUDAStream();
    const int64_t weight_count = weight.numel();
    const int64_t total_count = weight_count + x.numel();

    // Always convert the current operands; only GEMM metadata is cached.
    auto packed = torch::empty(
        {total_count}, x.options().dtype(at::kHalf));
    half* packed_ptr =
        reinterpret_cast<half*>(packed.data_ptr<at::Half>());

    const bool vector_pack =
        weight_count % 4 == 0 && x.numel() % 4 == 0 &&
        reinterpret_cast<uintptr_t>(weight.data_ptr<float>()) % 16 == 0 &&
        reinterpret_cast<uintptr_t>(x.data_ptr<float>()) % 16 == 0;

    if (vector_pack) {
        pack4_kernel<<<blocks_for(total_count / 4), 256, 0, stream>>>(
            reinterpret_cast<const float4*>(weight.data_ptr<float>()),
            reinterpret_cast<const float4*>(x.data_ptr<float>()),
            reinterpret_cast<uint2*>(packed_ptr),
            weight_count / 4, total_count / 4);
    } else {
        pack_scalar_kernel<<<blocks_for(total_count), 256, 0, stream>>>(
            weight.data_ptr<float>(), x.data_ptr<float>(),
            packed_ptr, weight_count, total_count);
    }
    C10_CUDA_KERNEL_LAUNCH_CHECK();

    auto& plan = get_plan(x.get_device(), m, n, k);
    const float alpha = 1.0f;
    const float beta = 0.0f;
    cublasStatus_t status = CUBLAS_STATUS_NOT_SUPPORTED;

    if (plan.available) {
        auto workspace = torch::empty(
            {static_cast<int64_t>(plan.workspace_size)},
            x.options().dtype(at::kByte));
        status = cublasLtMatmul(
            plan.handle, plan.operation, &alpha,
            packed_ptr, plan.a,
            packed_ptr + weight_count, plan.b,
            &beta,
            output.data_ptr<float>(), plan.c,
            output.data_ptr<float>(), plan.c,
            &plan.algorithm,
            plan.workspace_size ? workspace.data_ptr() : nullptr,
            plan.workspace_size, stream);
    }

    if (status != CUBLAS_STATUS_SUCCESS) {
        const auto handle = at::cuda::getCurrentCUDABlasHandle();
        check_blas(cublasGemmEx(
            handle, CUBLAS_OP_T, CUBLAS_OP_N,
            n, m, k, &alpha,
            packed_ptr, CUDA_R_16F, k,
            packed_ptr + weight_count, CUDA_R_16F, k,
            &beta,
            output.data_ptr<float>(), CUDA_R_32F, n,
            CUBLAS_COMPUTE_32F, CUBLAS_GEMM_DEFAULT_TENSOR_OP));
    }

    const int64_t count = output.numel();
    const bool vector_activation =
        n % 4 == 0 &&
        reinterpret_cast<uintptr_t>(bias.data_ptr<float>()) % 16 == 0 &&
        reinterpret_cast<uintptr_t>(add.data_ptr<float>()) % 16 == 0;

    if (vector_activation) {
        activate4_kernel<<<blocks_for(count / 4), 256, 0, stream>>>(
            reinterpret_cast<float4*>(output.data_ptr<float>()),
            reinterpret_cast<const float4*>(bias.data_ptr<float>()),
            reinterpret_cast<const float4*>(add.data_ptr<float>()),
            count / 4, n / 4);
    } else {
        activate_scalar_kernel<<<blocks_for(count), 256, 0, stream>>>(
            output.data_ptr<float>(), bias.data_ptr<float>(),
            add.data_ptr<float>(), count, n);
    }
    C10_CUDA_KERNEL_LAUNCH_CHECK();
    return output;
}
"""

_ops = load_inline(
    name="lt_packed_linear_fused_activations_v4",
    cpp_sources=_cpp_source,
    cuda_sources=_cuda_source,
    functions=["fused_linear_cuda"],
    extra_cflags=["-O3"],
    extra_cuda_cflags=["-O3"],
    extra_ldflags=["-lcublas", "-lcublasLt"],
    verbose=False,
)


class ModelNew(nn.Module):
    def __init__(self, in_features, out_features, add_value_shape):
        super().__init__()
        self.matmul = nn.Linear(in_features, out_features)
        self.add_value = nn.Parameter(torch.randn(add_value_shape))

    def forward(self, x):
        weight = self.matmul.weight
        bias = self.matmul.bias

        if (
            x.is_cuda
            and x.dtype == torch.float32
            and weight.dtype == torch.float32
            and bias.dtype == torch.float32
            and self.add_value.dtype == torch.float32
            and self.add_value.ndim == 1
            and self.add_value.numel() == weight.shape[0]
            and x.ndim >= 1
            and x.shape[-1] == weight.shape[1]
            and x.shape[-1] > 0
        ):
            output_shape = (*x.shape[:-1], weight.shape[0])
            return _ops.fused_linear_cuda(
                x.reshape(-1, x.shape[-1]).contiguous(),
                weight.contiguous(),
                bias.contiguous(),
                self.add_value.contiguous(),
            ).reshape(output_shape)

        x = self.matmul(x) + self.add_value
        x = torch.sigmoid(x) * x
        x = torch.tanh(x)
        x = F.gelu(x)
        return F.hardtanh(x, min_val=-1, max_val=1)
```
Result of evaluating it:
The solution is correct on the test inputs. Mean runtime 0.976 ms; the PyTorch reference (with TF32 enabled) takes 1.45 ms; speedup 1.486x.
Profiler, top device kernels of one forward pass of your solution:
| device kernel | total device time (us) | calls |
|---|---|---|
| void cutlass::Kernel2<cutlass_80_tensorop_s16816gemm_f16_128x128_32x4_tn_align8>(cutlass_8 | 560.8 | 1 |
| pack4_kernel(float4 const*, float4 const*, uint2*, long, long) | 338.0 | 1 |
| activate4_kernel(float4*, float4 const*, float4 const*, long, int) | 50.3 | 1 |
| Memset (Device) | 1.2 | 1 |

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.
