You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Simple model that performs a single matrix multiplication (C = A * B)
    """
    def __init__(self):
        super(Model, self).__init__()
    
    def forward(self, A: torch.Tensor, B: torch.Tensor) -> torch.Tensor:
        """
        Performs matrix multiplication.

        Args:
            A: Input tensor of shape (M, K).
            B: Input tensor of shape (K, N).

        Returns:
            Output tensor of shape (M, N).
        """
        return torch.matmul(A, B.T)

M = 1024 * 2
K = 4096 * 2
N = 2048 * 2

def get_inputs():
    A = torch.rand(M, K)
    B = torch.rand(N, K)
    return [A, B]

def get_init_inputs():
    return []  # No special initialization inputs needed
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 3 of 6 for this task. Your previous solution (turn 2) was:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
from torch.utils.cpp_extension import load_inline

# Strategy: the PyTorch reference uses TF32 tensor cores (cuBLAS), so a
# plain FP32 SIMT kernel cannot compete. Instead we:
#   1. Convert A (M,K) and B (N,K) from fp32 to fp16 with a fast
#      vectorized kernel (fp16 has the same 10-bit mantissa as TF32, so
#      accuracy is on par with the TF32 reference).
#   2. Run a custom fp16 tensor-core GEMM (fp32 accumulate) computing
#      C = A @ B^T, using:
#        - mma.sync.aligned.m16n8k16 PTX tensor-core instructions
#        - ldmatrix.x4 shared-memory operand loads
#        - XOR-swizzled shared layout (conflict-free, no padding waste)
#        - 4-stage cp.async software pipeline
#        - 128x128 CTA tile, 64x32 warp tile, K-tile 64
#        - L2-friendly grouped CTA rasterization
cuda_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cuda_pipeline.h>
#include <stdint.h>

#define BM 128
#define BN 128
#define BK 64
#define STAGES 4
#define GROUPN 8
#define NTHREADS 256

// ---------------------------------------------------------------------------
// fp32 -> fp16 conversion kernel (float4 loads, 8B stores)
// ---------------------------------------------------------------------------
__global__ void f32_to_f16_kernel(const float4* __restrict__ in,
                                  uint2* __restrict__ out,
                                  const long long n4) {
    long long i = (long long)blockIdx.x * blockDim.x + threadIdx.x;
    if (i < n4) {
        float4 v = in[i];
        __half2 h0 = __floats2half2_rn(v.x, v.y);
        __half2 h1 = __floats2half2_rn(v.z, v.w);
        uint2 o;
        o.x = *reinterpret_cast<unsigned*>(&h0);
        o.y = *reinterpret_cast<unsigned*>(&h1);
        out[i] = o;
    }
}

// ---------------------------------------------------------------------------
// Tensor-core GEMM: C(M,N) = A(M,K) @ B(N,K)^T, A/B fp16, C fp32.
// Requires M%128==0, N%128==0, K%64==0.
// ---------------------------------------------------------------------------
__global__ void __launch_bounds__(NTHREADS)
hgemm_tensor_op(const half* __restrict__ A, const half* __restrict__ B,
                float* __restrict__ C, const int M, const int N, const int K) {
    extern __shared__ __align__(16) char smem[];
    half* As = reinterpret_cast<half*>(smem);                    // [STAGES][BM][BK]
    half* Bs = reinterpret_cast<half*>(smem) + STAGES * BM * BK; // [STAGES][BN][BK]

    const int tid = threadIdx.x;
    const int lane = tid & 31;
    const int warp = tid >> 5;
    const int warp_m = warp >> 2;   // 0..1 (64 rows each)
    const int warp_n = warp & 3;    // 0..3 (32 cols each)

    // Grouped rasterization for L2 reuse
    const int grid_m = M / BM;
    const int grid_n = N / BN;
    const int bid = blockIdx.x;
    const int group_size = GROUPN * grid_m;
    const int group_id = bid / group_size;
    const int first_n = group_id * GROUPN;
    const int gsz = min(GROUPN, grid_n - first_n);
    const int rem = bid - group_id * group_size;
    const int tile_n = first_n + (rem % gsz);
    const int tile_m = rem / gsz;
    const int m0 = tile_m * BM;
    const int n0 = tile_n * BN;

    const int numTiles = K / BK;

    // Global->shared tile loader (cp.async, XOR swizzle on 16B chunks)
    auto issue_tile = [&](int kt, int stage) {
        const int k0 = kt * BK;
        half* As_s = As + stage * BM * BK;
        half* Bs_s = Bs + stage * BN * BK;
        #pragma unroll
        for (int i = 0; i < 4; ++i) {
            int idx = tid + i * NTHREADS;       // 0..1023
            int r = idx >> 3, c = idx & 7;
            int pc = c ^ (r & 7);
            const half* srcA = A + (long long)(m0 + r) * K + k0 + c * 8;
            const half* srcB = B + (long long)(n0 + r) * K + k0 + c * 8;
            __pipeline_memcpy_async(As_s + r * BK + pc * 8, srcA, 16);
            __pipeline_memcpy_async(Bs_s + r * BK + pc * 8, srcB, 16);
        }
    };

    #pragma unroll
    for (int s = 0; s < STAGES - 1; ++s) {
        if (s < numTiles) issue_tile(s, s);
        __pipeline_commit();
    }

    const uint32_t As_base = (uint32_t)__cvta_generic_to_shared(As);
    const uint32_t Bs_base = (uint32_t)__cvta_generic_to_shared(Bs);

    // ldmatrix A lane offsets: rows (lane&15), k halves 0/8 by bit4
    const int a_row = warp_m * 64 + (lane & 15);
    const int a_kh  = ((lane & 16) ? 8 : 0);
    // ldmatrix B lane offsets: n rows by bits (bit4, 0..7), k halves by bit3
    const int b_row = warp_n * 32 + ((lane & 16) ? 8 : 0) + (lane & 7);
    const int b_kh  = ((lane & 8) ? 8 : 0);

    float acc[4][4][4];
    #pragma unroll
    for (int i = 0; i < 4; ++i)
        #pragma unroll
        for (int j = 0; j < 4; ++j)
            #pragma unroll
            for (int r = 0; r < 4; ++r) acc[i][j][r] = 0.0f;

    for (int kt = 0; kt < numTiles; ++kt) {
        __pipeline_wait_prior(STAGES - 2);
        __syncthreads();

        int ktn = kt + STAGES - 1;
        if (ktn < numTiles) issue_tile(ktn, ktn % STAGES);
        __pipeline_commit();

        const uint32_t a_st = As_base + (uint32_t)((kt % STAGES) * (BM * BK * 2));
        const uint32_t b_st = Bs_base + (uint32_t)((kt % STAGES) * (BN * BK * 2));

        #pragma unroll
        for (int ks = 0; ks < BK; ks += 16) {
            uint32_t afr[4][4];
            uint32_t bfr[4][2];
            #pragma unroll
            for (int mi = 0; mi < 4; ++mi) {
                int r = a_row + mi * 16;
                int chunk = ((ks + a_kh) >> 3) ^ (r & 7);
                uint32_t addr = a_st + (uint32_t)(r * (BK * 2) + chunk * 16);
                asm volatile(
                    "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0,%1,%2,%3}, [%4];\n"
                    : "=r"(afr[mi][0]), "=r"(afr[mi][1]), "=r"(afr[mi][2]), "=r"(afr[mi][3])
                    : "r"(addr));
            }
            #pragma unroll
            for (int np = 0; np < 2; ++np) {
                int r = b_row + np * 16;
                int chunk = ((ks + b_kh) >> 3) ^ (r & 7);
                uint32_t addr = b_st + (uint32_t)(r * (BK * 2) + chunk * 16);
                uint32_t t0, t1, t2, t3;
                asm volatile(
                    "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0,%1,%2,%3}, [%4];\n"
                    : "=r"(t0), "=r"(t1), "=r"(t2), "=r"(t3)
                    : "r"(addr));
                bfr[np * 2][0] = t0;     bfr[np * 2][1] = t1;
                bfr[np * 2 + 1][0] = t2; bfr[np * 2 + 1][1] = t3;
            }
            #pragma unroll
            for (int mi = 0; mi < 4; ++mi) {
                #pragma unroll
                for (int ni = 0; ni < 4; ++ni) {
                    asm volatile(
                        "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 "
                        "{%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%0,%1,%2,%3};\n"
                        : "+f"(acc[mi][ni][0]), "+f"(acc[mi][ni][1]),
                          "+f"(acc[mi][ni][2]), "+f"(acc[mi][ni][3])
                        : "r"(afr[mi][0]), "r"(afr[mi][1]), "r"(afr[mi][2]), "r"(afr[mi][3]),
                          "r"(bfr[ni][0]), "r"(bfr[ni][1]));
                }
            }
        }
    }

    const int gid = lane >> 2;
    const int tig = lane & 3;
    #pragma unroll
    for (int mi = 0; mi < 4; ++mi) {
        int gr = m0 + warp_m * 64 + mi * 16 + gid;
        #pragma unroll
        for (int ni = 0; ni < 4; ++ni) {
            int gc = n0 + warp_n * 32 + ni * 8 + tig * 2;
            float2* p0 = reinterpret_cast<float2*>(C + (long long)gr * N + gc);
            *p0 = make_float2(acc[mi][ni][0], acc[mi][ni][1]);
            float2* p1 = reinterpret_cast<float2*>(C + (long long)(gr + 8) * N + gc);
            *p1 = make_float2(acc[mi][ni][2], acc[mi][ni][3]);
        }
    }
}

// ---------------------------------------------------------------------------
// Host wrappers
// ---------------------------------------------------------------------------
static inline void convert_to_half(torch::Tensor src, torch::Tensor dst,
                                   cudaStream_t stream) {
    long long n4 = src.numel() / 4;
    int threads = 256;
    long long blocks = (n4 + threads - 1) / threads;
    f32_to_f16_kernel<<<(unsigned)blocks, threads, 0, stream>>>(
        reinterpret_cast<const float4*>(src.data_ptr<float>()),
        reinterpret_cast<uint2*>(dst.data_ptr<at::Half>()), n4);
}

torch::Tensor matmul_a_bT_cuda(torch::Tensor A, torch::Tensor B) {
    const int64_t M = A.size(0);
    const int64_t K = A.size(1);
    const int64_t N = B.size(0);

    auto Ah = torch::empty({M, K}, A.options().dtype(at::kHalf));
    auto Bh = torch::empty({N, K}, A.options().dtype(at::kHalf));
    auto C = torch::empty({M, N}, A.options());

    cudaStream_t stream = at::cuda::getCurrentCUDAStream();
    convert_to_half(A, Ah, stream);
    convert_to_half(B, Bh, stream);

    static bool configured = [] {
        cudaFuncSetAttribute(hgemm_tensor_op,
                             cudaFuncAttributeMaxDynamicSharedMemorySize,
                             STAGES * (BM + BN) * BK * 2);
        return true;
    }();
    (void)configured;

    const size_t smem = STAGES * (BM + BN) * BK * 2;
    const int grid = (int)((M / BM) * (N / BN));
    hgemm_tensor_op<<<grid, NTHREADS, smem, stream>>>(
        reinterpret_cast<const half*>(Ah.data_ptr<at::Half>()),
        reinterpret_cast<const half*>(Bh.data_ptr<at::Half>()),
        C.data_ptr<float>(), (int)M, (int)N, (int)K);

    return C;
}
"""

cpp_source = "torch::Tensor matmul_a_bT_cuda(torch::Tensor A, torch::Tensor B);"

_matmul_ext = load_inline(
    name="hgemm_a_bT_ext_v2",
    cpp_sources=cpp_source,
    cuda_sources=cuda_source,
    functions=["matmul_a_bT_cuda"],
    verbose=False,
    extra_cflags=["-O3"],
    extra_cuda_cflags=["-O3"],
)


class ModelNew(nn.Module):
    """
    Optimized C = A @ B^T using custom CUDA kernels:
    fused fp32->fp16 conversion + a pipelined tensor-core (mma.m16n8k16)
    GEMM with fp32 accumulation.
    """
    def __init__(self):
        super(ModelNew, self).__init__()
        self._op = _matmul_ext

    def forward(self, A: torch.Tensor, B: torch.Tensor) -> torch.Tensor:
        if (
            A.is_cuda and B.is_cuda
            and A.dtype == torch.float32 and B.dtype == torch.float32
            and A.dim() == 2 and B.dim() == 2
            and A.size(1) == B.size(1)
            and A.is_contiguous() and B.is_contiguous()
            and A.size(0) % 128 == 0
            and B.size(0) % 128 == 0
            and A.size(1) % 64 == 0
            and A.numel() % 4 == 0 and B.numel() % 4 == 0
        ):
            return self._op.matmul_a_bT_cuda(A, B)
        return torch.matmul(A, B.t())
```
Result of evaluating it:
The solution is correct on the test inputs. Mean runtime 1 ms; the PyTorch reference (with TF32 enabled) takes 1.15 ms; speedup 1.150x.
Profiler, top device kernels of one forward pass of your solution:
| device kernel | total device time (us) | calls |
|---|---|---|
| hgemm_tensor_op(__half const*, __half const*, float*, int, int, int) | 755.5 | 1 |
| f32_to_f16_kernel(float4 const*, uint2*, long long) | 226.8 | 2 |

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.
