You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Performs a transposed 2D convolution with square input and square kernel.

    Args:
        in_channels (int): Number of channels in the input tensor.
        out_channels (int): Number of channels produced by the convolution.
        kernel_size (int): Size of the square convolution kernel.
        stride (int, optional): Stride of the convolution. Defaults to 1.
        padding (int, optional): Padding applied to the input. Defaults to 0.
        output_padding (int, optional): Additional size added to one side of the output shape. Defaults to 0.
        groups (int, optional): Number of blocked connections from input channels to output channels. Defaults to 1.
        bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.
    """
    def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):
        super(Model, self).__init__()
        self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding, groups=groups, bias=bias)

    def forward(self, x: torch.Tensor) -> torch.Tensor:
        """
        Performs the transposed 2D convolution.

        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, in_channels, height, width).

        Returns:
            torch.Tensor: Output tensor of shape (batch_size, out_channels, height_out, width_out).
        """
        return self.conv_transpose2d(x)

# Test code
batch_size = 8
in_channels = 64  # double channels for heavier compute
out_channels = 64
kernel_size = 3
# larger square input
height = 1024
width = 1024

def get_inputs():
    x = torch.rand(batch_size, in_channels, height, width)
    return [x]

def get_init_inputs():
    return [in_channels, out_channels, kernel_size]  # Provide in_channels, out_channels, kernel_size for initialization
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 6 of 6 for this task. Your previous solution (turn 5) was:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# ----------------------------------------------------------------------------------
# ConvTranspose2d (stride=1, K=3, C=OC=64) accelerated with a custom tensor-core
# CUDA kernel.
#
# Math: ConvTranspose2d(stride=1, padding=p, kernel=K, groups=1) is exactly a
# cross-correlation with spatially flipped, channel-swapped weights:
#     out[b,o,y,x] = sum_{c,u,v} x[b,c,y+u-p',x+v-p'] * wt[u,v,o,c]
#     wt[u,v,o,c]  = w[c,o,K-1-u,K-1-v],   p' = K-1-p
#
# Implementation: implicit GEMM with WMMA (fp16 inputs, fp32 accumulate),
# keeping everything in NCHW:
#   * one cast kernel converts x (fp32 NCHW) into a zero-padded fp16 buffer
#     [B, C, H+4, Wp] (fully coalesced float4 -> half2);
#   * the GEMM kernel treats M = out-channels (64), N = output pixels along a
#     row, K = 9 taps x 64 channels. B-fragments (input pixels) are read
#     straight from the padded NCHW buffer via row_major fragments with
#     ldm = Hp*Wp, A-fragments (weights) are L1-resident, and accumulators are
#     stored directly to the fp32 NCHW output. Edge tiles go through a shared
#     memory staging buffer with bounds-checked stores.
# ----------------------------------------------------------------------------------

cuda_src = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <mma.h>

using namespace nvcuda;

#define TN 256
#define THREADS 128
#define SMEM_BYTES (64 * 64 * 4 * 4)   // 4 warps x 64x64 floats = 64 KB

// ------------------------- fp32 -> fp16 into padded buffer ----------------------
// x : [B, C, H, W]  ->  xp : [B, C, Hp, Wp] with data placed at (y+2, x+2).
__global__ void cast_pad_kernel(const float* __restrict__ x,
                                half* __restrict__ xp,
                                int H, int W4, int Hp, long Wp, long HW4) {
    const long t = blockIdx.x * (long)blockDim.x + threadIdx.x;
    if (t >= HW4) return;
    const int c = blockIdx.y;
    const int b = blockIdx.z;
    const int y  = (int)(t / W4);
    const int x4 = (int)(t - (long)y * W4);

    const long bc = (long)b * gridDim.y + c;
    const float* xrow = x + (bc * H + y) * (long)(W4 * 4) + x4 * 4;
    const float4 v = *reinterpret_cast<const float4*>(xrow);

    half* orow = xp + (bc * Hp + (y + 2)) * Wp + (x4 * 4 + 2);
    __half2 h0 = __floats2half2_rn(v.x, v.y);
    __half2 h1 = __floats2half2_rn(v.z, v.w);
    orow[0] = __low2half(h0);
    orow[1] = __high2half(h0);
    orow[2] = __low2half(h1);
    orow[3] = __high2half(h1);
}

// zero only the non-data region of xp (halo + tile-overhang columns).
__global__ void zero_halo_kernel(half* __restrict__ xp,
                                 int H, int W, int Hp, long Wp) {
    const long bc = blockIdx.y;                    // b*C + c
    const int yy  = blockIdx.x * blockDim.y + threadIdx.y;
    if (yy >= Hp) return;
    half* row = xp + (bc * Hp + yy) * Wp;
    int start, count;
    if (yy < 2 || yy >= H + 2) { start = 0;     count = (int)Wp; }
    else                       { start = W + 2; count = (int)(Wp - W - 2); }
    half2 z; z.x = __float2half(0.0f); z.y = z.x;
    for (int i = threadIdx.x; i < (count >> 1); i += blockDim.x)
        reinterpret_cast<half2*>(row + start)[i] = z;
}

// ------------------------------ GEMM kernel --------------------------------------
// xp  : [B, C, Hp, Wp] fp16 (zero halo)
// wt  : [9, OC, C] fp16
// out : [B, OC, OH, OW] fp32
// block: 64(M=oc) x 256(N=pixels) tile, 4 warps of 64x64. C == OC == 64.
__global__ void __launch_bounds__(THREADS) tconv_gemm_kernel(
    const half* __restrict__ xp,
    const half* __restrict__ wt,
    float* __restrict__ out,
    int OH, int OW, long Wp, long Sp, int tpr, int pad)
{
    extern __shared__ float Cs[];   // per-warp 64x64 staging (edge tiles only)

    const int tile = blockIdx.x;
    const int x0 = (tile % tpr) * TN;
    const int y  = tile / tpr;
    const int b  = blockIdx.z;

    const int warp = threadIdx.x >> 5;        // 0..3
    const int n0   = x0 + warp * 64;

    const long OHOW = (long)OH * (long)OW;
    const half* xb  = xp + (long)b * 64 * Sp;

    wmma::fragment<wmma::accumulator, 16, 16, 16, float> acc[4][4];
#pragma unroll
    for (int i = 0; i < 4; ++i)
#pragma unroll
        for (int j = 0; j < 4; ++j)
            wmma::fill_fragment(acc[i][j], 0.0f);

    const unsigned lds = (unsigned)Sp;
#pragma unroll
    for (int u = 0; u < 3; ++u) {
        const long yrow = (long)(y + u + pad) * Wp;
#pragma unroll
        for (int v = 0; v < 3; ++v) {
            const half* btap = xb + yrow + (n0 + v + pad);
            const half* atap = wt + (u * 3 + v) * 4096;
#pragma unroll
            for (int c0 = 0; c0 < 64; c0 += 16) {
                wmma::fragment<wmma::matrix_a, 16, 16, 16, half, wmma::row_major> a[4];
                wmma::fragment<wmma::matrix_b, 16, 16, 16, half, wmma::row_major> bb[4];
#pragma unroll
                for (int i = 0; i < 4; ++i)
                    wmma::load_matrix_sync(a[i], atap + i * 1024 + c0, 64);
#pragma unroll
                for (int j = 0; j < 4; ++j)
                    wmma::load_matrix_sync(bb[j], btap + (long)c0 * Sp + j * 16, lds);
#pragma unroll
                for (int i = 0; i < 4; ++i)
#pragma unroll
                    for (int j = 0; j < 4; ++j)
                        wmma::mma_sync(acc[i][j], a[i], bb[j], acc[i][j]);
            }
        }
    }

    float* obase = out + (long)b * 64 * OHOW + (long)y * OW + n0;
    if (x0 + TN <= OW) {
        // full tile: direct stores, 64B row segments
#pragma unroll
        for (int i = 0; i < 4; ++i) {
            float* orow = obase + (long)(i * 16) * OHOW;
#pragma unroll
            for (int j = 0; j < 4; ++j)
                wmma::store_matrix_sync(orow + j * 16, acc[i][j], OHOW,
                                        wmma::mem_row_major);
        }
    } else {
        // edge tile: stage through shared memory, bounds-checked stores
        float* cw = Cs + warp * 64 * 64;
#pragma unroll
        for (int i = 0; i < 4; ++i)
#pragma unroll
            for (int j = 0; j < 4; ++j)
                wmma::store_matrix_sync(cw + i * 16 * 64 + j * 16, acc[i][j], 64,
                                        wmma::mem_row_major);
        __syncwarp();
        const int valid = OW - n0;              // 1..64
        if (valid > 0) {
            const int lane = threadIdx.x & 31;
            for (int idx = lane; idx < 64 * valid; idx += 32) {
                const int m = idx / valid;
                const int n = idx - m * valid;
                obase[(long)m * OHOW + n] = cw[m * 64 + n];
            }
        }
    }
}

// --------------------------------- host wrapper ----------------------------------
torch::Tensor conv_transpose2d_fp16gemm(torch::Tensor x, torch::Tensor wt,
                                        int64_t pad) {
    TORCH_CHECK(x.is_cuda() && x.dtype() == torch::kFloat32, "x must be CUDA fp32");
    TORCH_CHECK(wt.is_cuda() && wt.dtype() == torch::kHalf, "wt must be CUDA fp16");
    const int B = x.size(0);
    const int C = x.size(1);
    const int H = x.size(2);
    const int W = x.size(3);
    const int OC = wt.size(1);
    TORCH_CHECK(C == 64 && OC == 64, "fast kernel requires C == OC == 64");
    TORCH_CHECK((W & 3) == 0, "W must be a multiple of 4");

    const int p  = (int)pad;
    const int OH = H + 2 - 2 * p;             // K = 3, stride = 1
    const int OW = W + 2 - 2 * p;
    TORCH_CHECK(OH > 0 && OW > 0, "invalid output size");

    const int Hp  = H + 4;
    const int tpr = (OW + TN - 1) / TN;
    const long Wp = (long)tpr * TN + 2;       // covers tile overhang reads
    const long Sp = (long)Hp * Wp;

    auto xp = torch::empty({(long)B * C * Sp}, x.options().dtype(torch::kHalf));
    auto stream = at::cuda::getCurrentCUDAStream();
    half* xp_ptr = reinterpret_cast<half*>(xp.data_ptr<at::Half>());

    {   // zero halo (rows: Hp per (b,c) plane)
        TORCH_CHECK(Hp <= 1024, "Hp too large");
        dim3 block(32, 32);
        dim3 grid((unsigned)((Hp + 31) / 32), (unsigned)(B * C));
        zero_halo_kernel<<<grid, block, 0, stream>>>(xp_ptr, H, W, Hp, Wp);
    }
    {   // cast + place data
        const int W4 = W / 4;
        const long HW4 = (long)H * W4;
        dim3 grid((unsigned)((HW4 + 255) / 256), (unsigned)C, (unsigned)B);
        cast_pad_kernel<<<grid, 256, 0, stream>>>(
            x.data_ptr<float>(), xp_ptr, H, W4, Hp, Wp, HW4);
    }

    auto out = torch::empty({B, OC, OH, OW}, x.options());

    static bool smem_configured = false;
    if (!smem_configured) {
        cudaFuncSetAttribute(tconv_gemm_kernel,
                             cudaFuncAttributeMaxDynamicSharedMemorySize,
                             SMEM_BYTES);
        smem_configured = true;
    }

    dim3 grid((unsigned)(tpr * OH), 1, (unsigned)B);
    tconv_gemm_kernel<<<grid, THREADS, SMEM_BYTES, stream>>>(
        xp_ptr,
        reinterpret_cast<const half*>(wt.data_ptr<at::Half>()),
        out.data_ptr<float>(),
        OH, OW, Wp, Sp, tpr, p);

    return out;
}
"""

cpp_src = "torch::Tensor conv_transpose2d_fp16gemm(torch::Tensor x, torch::Tensor wt, int64_t pad);"

_conv_mod = load_inline(
    name="conv_transpose2d_nchw_gemm_v4",
    cpp_sources=cpp_src,
    cuda_sources=cuda_src,
    functions=["conv_transpose2d_fp16gemm"],
    verbose=False,
    extra_cuda_cflags=["-O3", "--use_fast_math"],
)


class ModelNew(nn.Module):
    """
    ConvTranspose2d accelerated with a custom tensor-core implicit-GEMM CUDA
    kernel (fast path: stride=1, groups=1, kernel 3x3, padding in {0,1,2},
    output_padding=0, in_channels = out_channels = 64, no bias, CUDA fp32
    input, width a multiple of 4). All other configurations fall back to the
    cuDNN implementation.
    """

    def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1,
                 padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):
        super(ModelNew, self).__init__()
        self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,
                                                   stride=stride, padding=padding,
                                                   output_padding=output_padding,
                                                   groups=groups, bias=bias)
        self.stride = stride
        self.padding = padding
        self.output_padding = output_padding
        self.groups = groups
        self.kernel_size = kernel_size

        self._fast = (stride == 1 and groups == 1 and kernel_size == 3
                      and output_padding == 0 and 0 <= padding <= 2
                      and in_channels == 64 and out_channels == 64)

    def forward(self, x: torch.Tensor) -> torch.Tensor:
        w = self.conv_transpose2d
        if (self._fast and w.bias is None and x.is_cuda
                and x.dtype == torch.float32 and x.dim() == 4 and x.size(1) == 64
                and (x.size(3) & 3) == 0):
            # rearranged weights wt[u,v,o,c] = w[c,o,2-u,2-v], rebuilt every
            # call (tiny: 36k elements) so weight updates are always honored.
            wt = (w.weight.detach()
                  .permute(2, 3, 1, 0)          # [3,3,OC,C]
                  .flip(0, 1)                   # spatial flip
                  .contiguous()
                  .view(9, 64, 64)
                  .to(torch.float16))
            return _conv_mod.conv_transpose2d_fp16gemm(x.contiguous(), wt, self.padding)
        return F.conv_transpose2d(x, w.weight, w.bias, self.stride, self.padding,
                                  self.output_padding, self.groups)
```
Result of evaluating it:
The solution compiled but failed at run time. Error output:
```
Hp too large
```

The fastest correct solution so far (0.703x speedup) is:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# ----------------------------------------------------------------------------------
# ConvTranspose2d (stride=1, K=3, C=OC=64) accelerated with a custom tensor-core
# CUDA kernel.
#
# Math: ConvTranspose2d(stride=1, padding=p, kernel=K, groups=1) is exactly a
# cross-correlation with spatially flipped, channel-swapped weights and padding
# p' = K-1-p:
#     out[b,o,y,x] = sum_{c,u,v} x[b,c,y+u-p',x+v-p'] * wf[u,v,c,o]
#     wf[u,v,c,o]  = w[c,o,K-1-u,K-1-v]
#
# Implementation: implicit GEMM with WMMA (fp16 inputs, fp32 accumulate).
#   * A tiled-transpose kernel converts x from NCHW(fp32) to NHWC(fp16) inside a
#     zero-padded halo buffer [B, HB, Wp, C] so every 16-channel GEMM-k slice is
#     contiguous and 128B aligned for any spatial shift. A fragments are read
#     straight from global memory (no im2col, no gather).
#   * Accumulators are staged through shared memory and written to the NCHW
#     output with plain coalesced stores.
# ----------------------------------------------------------------------------------

cuda_src = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <mma.h>

using namespace nvcuda;

#define TM 128
#define THREADS 128

// ---------------------- NCHW fp32 -> NHWC fp16 (halo buffer) ---------------------
// x : [B, C, H*W]  ->  xn : [B, HB, Wp, C], data rows [0,H), cols [XOFF, XOFF+W).
// block: (64,4) threads, 64x64 shared tile; requires C == 64 (guarded on host).
__global__ void nchw2nhwc_kernel(const float* __restrict__ x,
                                 half* __restrict__ xn,
                                 int B, int C, int H, int W,
                                 int HB, int Wp, int XOFF) {
    __shared__ float tile[64][65];
    const long S = (long)H * (long)W;
    const int s0 = blockIdx.x * 64;
    const int c0 = blockIdx.y * 64;
    const int b  = blockIdx.z;
    const int tx = threadIdx.x;   // 0..63
    const int ty = threadIdx.y;   // 0..3

    const float* xb = x + (long)b * C * S;
    // coalesced read along s
#pragma unroll
    for (int i = 0; i < 16; ++i) {
        const int c = c0 + ty + 4 * i;
        const int s = s0 + tx;
        float v = 0.0f;
        if (c < C && s < S) v = xb[(long)c * S + s];
        tile[ty + 4 * i][tx] = v;
    }
    __syncthreads();

    half* xnb = xn + (long)b * HB * Wp * C;
    const int c = c0 + tx;
    if (c >= C) return;

    // coalesced write along c; walk s in strides of 4 with cheap row tracking
    int s  = s0 + ty;
    int y  = s / W;
    int xx = s - y * W;
#pragma unroll
    for (int i = 0; i < 16; ++i) {
        if (s < S) {
            xnb[((long)y * Wp + XOFF + xx) * C + c] =
                __float2half(tile[tx][ty + 4 * i]);
        }
        s += 4;
        xx += 4;
        while (xx >= W) { xx -= W; ++y; }
    }
}

// zero everything in the halo buffer that is not the data region (C == 64).
__global__ void zero_halo_kernel(half* __restrict__ xn,
                                 int B, int H, int W,
                                 int HB, int Wp, int XOFF) {
    const int y = blockIdx.x;   // 0..HB-1
    const int b = blockIdx.y;
    half* row = xn + ((long)b * HB + y) * (long)Wp * 64;
    if (y < H) {
        const int n = (Wp - W) * 64;   // halo columns of a data row
        for (int idx = threadIdx.x; idx < n; idx += blockDim.x) {
            const int hc  = idx >> 6;
            const int c   = idx & 63;
            const int col = (hc < XOFF) ? hc : (XOFF + W + hc - XOFF);
            row[(long)col * 64 + c] = __float2half(0.0f);
        }
    } else {
        const int n = Wp * 64;         // full bottom rows
        for (int idx = threadIdx.x; idx < n; idx += blockDim.x) {
            row[idx] = __float2half(0.0f);
        }
    }
}

// ----------------------------- WMMA conv kernel ----------------------------------
// block: 4 warps -> out[b, 0:OC, y, x0:x0+TM]; requires C == OC == 64.
__global__ void __launch_bounds__(THREADS) imtconv_wmma_kernel(
    const half* __restrict__ xn,   // [B, HB, Wp, C]
    const half* __restrict__ w2,   // [9, C, OC] fp16
    float* __restrict__ out,       // [B, OC, OH, OW]
    int B, int C, int W, int OC, int OH, int OW,
    int HB, int Wp, int XOFF, int pprime, int tiles_per_row)
{
    extern __shared__ float Cs[];  // TM x OC staging (layout [o][m])

    const int tile_id = blockIdx.x;
    const int y   = tile_id % OH;
    const int tmp = tile_id / OH;
    const int ti  = tmp % tiles_per_row;
    const int b   = tmp / tiles_per_row;
    const int x0  = ti * TM;

    const int warp = threadIdx.x >> 5;
    const int m_base = warp * 32;

    wmma::fragment<wmma::accumulator, 16, 16, 16, float> acc[2][4];
#pragma unroll
    for (int i = 0; i < 2; ++i)
#pragma unroll
        for (int j = 0; j < 4; ++j)
            wmma::fill_fragment(acc[i][j], 0.0f);

    const half* xb = xn + (long)b * HB * Wp * C;
    const long OHOW = (long)OH * (long)OW;

    for (int u = 0; u < 3; ++u) {
        const int yy = y + u - pprime;
        if ((unsigned)yy >= (unsigned)HB) continue;   // outside halo buffer
        const half* xrow = xb + ((long)yy * Wp + XOFF + x0 + m_base) * C;
        const half* wu = w2 + (long)u * 3 * C * OC;
#pragma unroll
        for (int v = 0; v < 3; ++v) {
            const half* wuv = wu + (long)v * C * OC;
            const long aoff = (long)(v - pprime) * C;
#pragma unroll
            for (int c0 = 0; c0 < 64; c0 += 16) {
                wmma::fragment<wmma::matrix_b, 16, 16, 16, half, wmma::row_major> bfrag[4];
#pragma unroll
                for (int nf = 0; nf < 4; ++nf)
                    wmma::load_matrix_sync(bfrag[nf], wuv + (long)c0 * OC + nf * 16, OC);
                const half* aptr = xrow + aoff + c0;
#pragma unroll
                for (int mf = 0; mf < 2; ++mf) {
                    wmma::fragment<wmma::matrix_a, 16, 16, 16, half, wmma::row_major> afrag;
                    wmma::load_matrix_sync(afrag, aptr + mf * 16 * C, C);
#pragma unroll
                    for (int nf = 0; nf < 4; ++nf)
                        wmma::mma_sync(acc[mf][nf], afrag, bfrag[nf], acc[mf][nf]);
                }
            }
        }
    }

    // stage accumulators through shared memory: Cs[o * TM + m]
#pragma unroll
    for (int mf = 0; mf < 2; ++mf)
#pragma unroll
        for (int nf = 0; nf < 4; ++nf)
            wmma::store_matrix_sync(Cs + (nf * 16) * TM + warp * 32 + mf * 16,
                                    acc[mf][nf], TM, wmma::mem_col_major);
    __syncthreads();

    // coalesced NCHW stores; correct for partial (edge) tiles as well
    const int m_valid = min(TM, OW - x0);
    const long bbase = (long)b * OC * OHOW + (long)y * OW + x0;
    for (int o = 0; o < OC; ++o) {
        const float* srow = Cs + o * TM;
        float* orow = out + bbase + (long)o * OHOW;
        for (int m = threadIdx.x; m < m_valid; m += THREADS)
            orow[m] = srow[m];
    }
}

// --------------------------------- host wrapper ----------------------------------
torch::Tensor conv_transpose2d_wmma(torch::Tensor x, torch::Tensor w2,
                                    int64_t pad) {
    TORCH_CHECK(x.is_cuda() && x.dtype() == torch::kFloat32, "x must be CUDA fp32");
    TORCH_CHECK(w2.is_cuda() && w2.dtype() == torch::kHalf, "w2 must be CUDA fp16");
    const int B  = x.size(0);
    const int C  = x.size(1);
    const int H  = x.size(2);
    const int W  = x.size(3);
    const int OC = w2.size(2);
    TORCH_CHECK(C == 64 && OC == 64, "fast kernel requires C == OC == 64");

    const int pprime = 2 - (int)pad;          // K = 3
    const int OH = H + 2 * pprime - 2;
    const int OW = W + 2 * pprime - 2;
    TORCH_CHECK(OH > 0 && OW > 0, "invalid output size");

    const int HB   = H + 2;
    const int XOFF = 2;
    const int Wp   = W + TM + 2 * XOFF + 8;   // extra slack for edge-tile reads

    auto xn = torch::empty({(long)B * HB * Wp * C},
                           x.options().dtype(torch::kHalf));
    auto stream = at::cuda::getCurrentCUDAStream();
    half* xn_ptr = reinterpret_cast<half*>(xn.data_ptr<at::Half>());

    // zero the halo region
    {
        dim3 grid((unsigned)HB, (unsigned)B);
        zero_halo_kernel<<<grid, 256, 0, stream>>>(xn_ptr, B, H, W, HB, Wp, XOFF);
    }
    // transpose + cast into the halo buffer
    {
        const long S = (long)H * W;
        dim3 block(64, 4);
        dim3 grid((unsigned)((S + 63) / 64), (unsigned)((C + 63) / 64),
                  (unsigned)B);
        nchw2nhwc_kernel<<<grid, block, 0, stream>>>(
            x.data_ptr<float>(), xn_ptr, B, C, H, W, HB, Wp, XOFF);
    }

    auto out = torch::empty({B, OC, OH, OW}, x.options());

    const int tiles_per_row = (OW + TM - 1) / TM;
    const long blocks = (long)B * tiles_per_row * OH;
    const size_t sh = (size_t)TM * OC * sizeof(float);   // 32 KB

    imtconv_wmma_kernel<<<(unsigned)blocks, THREADS, sh, stream>>>(
        xn_ptr,
        reinterpret_cast<const half*>(w2.data_ptr<at::Half>()),
        out.data_ptr<float>(),
        B, C, W, OC, OH, OW, HB, Wp, XOFF, pprime, tiles_per_row);

    return out;
}
"""

cpp_src = "torch::Tensor conv_transpose2d_wmma(torch::Tensor x, torch::Tensor w2, int64_t pad);"

_conv_mod = load_inline(
    name="conv_transpose2d_wmma_nhwc_v3",
    cpp_sources=cpp_src,
    cuda_sources=cuda_src,
    functions=["conv_transpose2d_wmma"],
    verbose=False,
    extra_cuda_cflags=["-O3", "--use_fast_math"],
)


class ModelNew(nn.Module):
    """
    ConvTranspose2d accelerated with a custom tensor-core implicit-GEMM CUDA
    kernel (fast path: stride=1, groups=1, kernel 3x3, padding in {0,1,2},
    output_padding=0, in_channels = out_channels = 64, no bias, CUDA fp32
    input). All other configurations fall back to the cuDNN implementation.
    """

    def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1,
                 padding: int = 0, output_padding: int = 0, groups: int = 1, bias: bool = False):
        super(ModelNew, self).__init__()
        self.conv_transpose2d = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,
                                                   stride=stride, padding=padding,
                                                   output_padding=output_padding,
                                                   groups=groups, bias=bias)
        self.stride = stride
        self.padding = padding
        self.output_padding = output_padding
        self.groups = groups
        self.kernel_size = kernel_size

        self._fast = (stride == 1 and groups == 1 and kernel_size == 3
                      and output_padding == 0 and 0 <= padding <= 2
                      and in_channels == 64 and out_channels == 64)

    def forward(self, x: torch.Tensor) -> torch.Tensor:
        w = self.conv_transpose2d
        if (self._fast and w.bias is None and x.is_cuda
                and x.dtype == torch.float32 and x.dim() == 4 and x.size(1) == 64):
            # rearranged weights wf[u,v,c,o] = w[c,o,2-u,2-v], rebuilt every
            # call (tiny: 36k elements) so weight updates are always honored.
            w2 = (w.weight.detach()
                  .permute(2, 3, 0, 1)          # [3,3,C,OC]
                  .flip(0, 1)                   # spatial flip
                  .contiguous()
                  .to(torch.float16))
            return _conv_mod.conv_transpose2d_wmma(x.contiguous(), w2, self.padding)
        return F.conv_transpose2d(x, w.weight, w.bias, self.stride, self.padding,
                                  self.output_padding, self.groups)
```

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.
