You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Performs a standard 2D convolution operation with square input and asymmetric kernel, with dilation and padding.

    Args:
        in_channels (int): Number of channels in the input tensor.
        out_channels (int): Number of channels produced by the convolution.
        kernel_size (tuple): Size of the convolution kernel (height, width). 
        stride (int, optional): Stride of the convolution. Defaults to 1.
        padding (tuple, optional): Padding applied to the input (top/bottom, left/right). Defaults to (0, 0).
        dilation (tuple, optional): Spacing between kernel elements (height, width). Defaults to (1, 1).
        bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.
    """
    def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple, stride: int = 1, padding: tuple = (0, 0), dilation: tuple = (1, 1), bias: bool = False):
        super(Model, self).__init__()
        self.conv2d = nn.Conv2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, bias=bias)
        
    def forward(self, x: torch.Tensor) -> torch.Tensor:
        """
        Performs the 2D convolution.

        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, in_channels, height, width).

        Returns:
            torch.Tensor: Output tensor of shape (batch_size, out_channels, height_out, width_out).
        """
        return self.conv2d(x)

# Test code
batch_size = 8
in_channels = 32
out_channels = 64
kernel_size = (5, 9)
width = 512
height = 512
stride = 1
padding = (2, 4)
dilation = (2, 3)

def get_inputs():
    x = torch.rand(batch_size, in_channels, height, width)
    return [x]

def get_init_inputs():
    return [in_channels, out_channels, kernel_size, stride, padding, dilation]
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 5 of 6 for this task. Your previous solution (turn 4) was:
```python
import torch
import torch.nn as nn
from torch.utils.cpp_extension import load_inline

_cuda_src = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>
#include <cstdint>

// Direct NCHW conv2d, stride=1, C=32, N=64, TF32 tensor cores.
// CTA: 128 threads (4 warps). Computes out[b, 0:64, H0:H0+8, W0:W0+16].
// x halo tile in smem: [c][hh 0..16][ww 0..39] (row 16 = pad for bank spread).
// weights staged per tap: [n][c] stride 36 (pre-rounded tf32).

#define XS_HH 680
#define XS_WW 40
#define XS_FLOATS (32 * XS_HH)
#define WT_STRIDE 36
#define WT_FLOATS (64 * WT_STRIDE)
#define SMEM_FLOATS (XS_FLOATS + WT_FLOATS)
#define NT 128

__device__ __forceinline__ float rnd_tf32(float x) {
    return __float_as_uint(__float_as_uint(x) & 0xffffe000u) == 0u ? x :
           __uint_as_float(((__float_as_uint(x) + 0x1000u) & 0xffffe000u) |
                           (__float_as_uint(x) & 0x80000000u & 0u));
}
// proper round-to-nearest tf32 via cvt instruction
__device__ __forceinline__ float cvt_tf32(float x) {
    uint32_t r;
    asm volatile("cvt.rna.tf32.f32 %0, %1;\n" : "=r"(r) : "f"(x));
    return __uint_as_float(r);
}

__device__ __forceinline__ void mma_tf32(float &d0, float &d1, float &d2, float &d3,
                                         uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3,
                                         uint32_t b0, uint32_t b1) {
    asm volatile(
        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 "
        "{%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%0,%1,%2,%3};\n"
        : "+f"(d0), "+f"(d1), "+f"(d2), "+f"(d3)
        : "r"(a0), "r"(a1), "r"(a2), "r"(a3), "r"(b0), "r"(b1));
}

__global__ void __launch_bounds__(NT)
conv2d_tf32_kernel(const float* __restrict__ x, const float* __restrict__ w,
                   const float* __restrict__ bias, float* __restrict__ out,
                   int Hin, int Win, int kh, int kw,
                   int dh, int dw, int ph, int pw) {
    extern __shared__ float smem[];
    float* Xs = smem;                 // [c][hh][ww], hh stride 680, ww stride 1
    float* Wt = smem + XS_FLOATS;     // [n][c], stride 36

    const int tid = threadIdx.x;
    const int lane = tid & 31;
    const int warp = tid >> 5;
    const int g = lane >> 2;          // 0..7
    const int t = lane & 3;           // 0..3

    const int H0 = blockIdx.x * 8;
    const int W0 = blockIdx.y * 16;
    const int b  = blockIdx.z;

    const long inHW = (long)Hin * Win;
    const float* xb = x + (long)b * 32 * inHW;

    // ---------------- load x halo tile: 32c x 16hh x 40ww ----------------
    // slots: 32*16*10 float4 = 5120; 128 threads -> 40 iters
    #pragma unroll
    for (int it = 0; it < 40; ++it) {
        int idx = it * NT + tid;
        int ww4 = idx % 10;
        int hh  = (idx / 10) & 15;
        int c   = idx / 160;
        int gh  = H0 - ph + hh;
        int gw  = W0 - pw + ww4 * 4;
        float4 v = make_float4(0.f, 0.f, 0.f, 0.f);
        if ((unsigned)gh < (unsigned)Hin && (unsigned)gw < (unsigned)Win) {
            v = *reinterpret_cast<const float4*>(xb + (long)c * inHW + (long)gh * Win + gw);
        }
        float4 d;
        d.x = cvt_tf32(v.x); d.y = cvt_tf32(v.y); d.z = cvt_tf32(v.z); d.w = cvt_tf32(v.w);
        *reinterpret_cast<float4*>(Xs + c * XS_HH + hh * XS_WW + ww4 * 4) = d;
    }
    __syncthreads();

    // ---------------- weight prefetch (registers), double buffered ----------------
    // thread handles (n,c): n = tid>>1, c = (tid&1)*16 + e, e = 0..15
    const int wn = tid >> 1;
    const int wc0 = (tid & 1) * 16;
    const long tap0 = (long)wn * 32 * kh * kw + wc0 * kh * kw;
    float wr[16];

    auto wload = [&](int tap) {
        const float* src = w + tap0 + tap;
        #pragma unroll
        for (int e = 0; e < 16; ++e) {
            wr[e] = cvt_tf32(__ldg(src + (long)e * kh * kw));
        }
    };

    const int ntaps = kh * kw;
    wload(0);

    // ---------------- accumulators ----------------
    float acc[2][8][4];
    #pragma unroll
    for (int mt = 0; mt < 2; ++mt)
        #pragma unroll
        for (int nt = 0; nt < 8; ++nt)
            #pragma unroll
            for (int v = 0; v < 4; ++v) acc[mt][nt][v] = 0.f;

    // A-operand per-thread base: Xs[(k0+t)*680 + (2*warp+mt+?)*40 + g]
    const int a_t  = t * XS_HH + g;          // + k0*680 + hh*40
    const int a_t4 = a_t + 4 * XS_HH;
    const int hh40_0 = (2 * warp) * XS_WW;
    const int hh40_1 = (2 * warp + 1) * XS_WW;
    // B-operand per-thread base: Wt[g*36 + k0 + t]
    const int b_base = g * WT_STRIDE + t;

    for (int tap = 0; tap < ntaps; ++tap) {
        // stage weights
        #pragma unroll
        for (int e = 0; e < 16; ++e) {
            Wt[wn * WT_STRIDE + wc0 + e] = wr[e];
        }
        __syncthreads();
        if (tap + 1 < ntaps) wload(tap + 1);

        const int i = tap / kw;
        const int j = tap - i * kw;
        const int tap_base = i * dh * XS_WW + j * dw;

        #pragma unroll
        for (int ks = 0; ks < 4; ++ks) {
            const int k0 = ks * 8;
            // load A fragments for both m-tiles
            uint32_t a[2][4];
            {
                const float* p0 = Xs + tap_base + k0 * XS_HH + a_t + hh40_0;
                const float* p1 = Xs + tap_base + k0 * XS_HH + a_t + hh40_1;
                const float* p4 = Xs + tap_base + k0 * XS_HH + a_t4 + hh40_0;
                const float* p5 = Xs + tap_base + k0 * XS_HH + a_t4 + hh40_1;
                a[0][0] = __float_as_uint(p0[0]);
                a[0][1] = __float_as_uint(p0[8]);
                a[0][2] = __float_as_uint(p4[0]);
                a[0][3] = __float_as_uint(p4[8]);
                a[1][0] = __float_as_uint(p1[0]);
                a[1][1] = __float_as_uint(p1[8]);
                a[1][2] = __float_as_uint(p5[0]);
                a[1][3] = __float_as_uint(p5[8]);
            }
            // load B fragments and mma
            const float* bp = Wt + b_base + k0;
            #pragma unroll
            for (int nt = 0; nt < 8; ++nt) {
                uint32_t b0 = __float_as_uint(bp[nt * 8 * WT_STRIDE]);
                uint32_t b1 = __float_as_uint(bp[nt * 8 * WT_STRIDE + 4]);
                mma_tf32(acc[0][nt][0], acc[0][nt][1], acc[0][nt][2], acc[0][nt][3],
                         a[0][0], a[0][1], a[0][2], a[0][3], b0, b1);
                mma_tf32(acc[1][nt][0], acc[1][nt][1], acc[1][nt][2], acc[1][nt][3],
                         a[1][0], a[1][1], a[1][2], a[1][3], b0, b1);
            }
        }
        __syncthreads();
    }

    // ---------------- epilogue: stage via smem, coalesced store ----------------
    __syncthreads();  // all taps done; Xs no longer needed
    const float* biasp = bias;

    // write acc -> Xs staged as [n][hh][ww] with n-stride 132
    // c0:(m=g,n=2t) c1:(m=g,n=2t+1) c2:(m=g+8,n=2t) c3:(m=g+8,n=2t+1)
    #pragma unroll
    for (int mt = 0; mt < 2; ++mt) {
        const int hh = 2 * warp + mt;
        #pragma unroll
        for (int nt = 0; nt < 8; ++nt) {
            const int n0 = nt * 8 + 2 * t;
            float b0 = biasp ? biasp[n0] : 0.f;
            float b1 = biasp ? biasp[n0 + 1] : 0.f;
            float* s0 = Xs + n0 * 132 + hh * 16 + g;
            float* s1 = Xs + (n0 + 1) * 132 + hh * 16 + g;
            s0[0] = acc[mt][nt][0] + b0;
            s1[0] = acc[mt][nt][1] + b1;
            s0[8] = acc[mt][nt][2] + b0;
            s1[8] = acc[mt][nt][3] + b1;
        }
    }
    __syncthreads();

    // read back coalesced: slots 64n x 8hh x 4ww4 = 2048 float4; 128 thr -> 16 iters
    float* outb = out + (long)b * 64 * 512 * 512;
    #pragma unroll
    for (int it = 0; it < 16; ++it) {
        int idx = it * NT + tid;
        int ww4 = idx & 3;
        int hh  = (idx >> 2) & 7;
        int n   = idx >> 5;
        int gh = H0 + hh;
        int gw = W0 + ww4 * 4;
        if (gh < 512 && gw + 3 < 512) {
            const float4 v = *reinterpret_cast<const float4*>(Xs + n * 132 + hh * 16 + ww4 * 4);
            *reinterpret_cast<float4*>(outb + ((long)n * 512 + gh) * 512 + gw) = v;
        }
    }
}

torch::Tensor conv2d_forward(torch::Tensor x, torch::Tensor w, torch::Tensor bias,
                             int64_t ph, int64_t pw, int64_t dh, int64_t dw,
                             int64_t kh, int64_t kw, int64_t Ho, int64_t Wo) {
    auto xc = x.contiguous();
    auto wc = w.contiguous();
    const int Bc = (int)xc.size(0);
    auto out = torch::empty({Bc, 64, Ho, Wo}, xc.options());
    if (Bc == 0 || Ho == 0 || Wo == 0) return out;

    dim3 grid(Ho / 8, Wo / 16, Bc);
    const int smem = SMEM_FLOATS * 4;
    static int configured = 0;
    if (!configured) {
        cudaFuncSetAttribute(conv2d_tf32_kernel,
                             cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
        configured = 1;
    }
    const float* bias_ptr = (bias.defined() && bias.numel() > 0)
                                ? bias.data_ptr<float>() : nullptr;
    auto stream = at::cuda::getCurrentCUDAStream();
    conv2d_tf32_kernel<<<grid, NT, smem, stream>>>(
        xc.data_ptr<float>(), wc.data_ptr<float>(), bias_ptr, out.data_ptr<float>(),
        (int)xc.size(2), (int)xc.size(3), (int)kh, (int)kw,
        (int)dh, (int)dw, (int)ph, (int)pw);
    return out;
}
"""

_cpp_src = """
torch::Tensor conv2d_forward(torch::Tensor x, torch::Tensor w, torch::Tensor bias,
                             int64_t ph, int64_t pw, int64_t dh, int64_t dw,
                             int64_t kh, int64_t kw, int64_t Ho, int64_t Wo);
"""

_conv_ext = load_inline(
    name="conv2d_tf32_direct_v4",
    cpp_sources=_cpp_src,
    cuda_sources=_cuda_src,
    functions=["conv2d_forward"],
    verbose=False,
    extra_cuda_cflags=["-O3"],
)


def _pair(v):
    if isinstance(v, int):
        return (v, v)
    return (int(v[0]), int(v[1]))


class ModelNew(nn.Module):
    def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,
                 stride: int = 1, padding: tuple = (0, 0), dilation: tuple = (1, 1),
                 bias: bool = False):
        super(ModelNew, self).__init__()
        self.conv2d = nn.Conv2d(in_channels, out_channels, kernel_size,
                                stride=stride, padding=padding,
                                dilation=dilation, bias=bias)
        self._stride = _pair(stride)
        self._padding = _pair(padding)
        self._dilation = _pair(dilation)
        kh, kw = self.conv2d.weight.shape[2], self.conv2d.weight.shape[3]
        self._fast = (
            in_channels == 32 and out_channels == 64
            and self._stride == (1, 1)
            and (kh - 1) * self._dilation[0] <= 8
            and (kw - 1) * self._dilation[1] <= 24
        )
        self._empty_bias = None

    def forward(self, x: torch.Tensor) -> torch.Tensor:
        w = self.conv2d.weight
        if (self._fast and x.is_cuda and x.dtype == torch.float32
                and w.dtype == torch.float32 and x.dim() == 4
                and x.size(2) % 8 == 0 and x.size(3) % 16 == 0):
            ph, pw = self._padding
            dh, dw = self._dilation
            kh, kw = w.shape[2], w.shape[3]
            Ho = x.size(2) + 2 * ph - dh * (kh - 1)
            Wo = x.size(3) + 2 * pw - dw * (kw - 1)
            if Ho % 8 == 0 and Wo % 16 == 0 and Ho > 0 and Wo > 0:
                b = self.conv2d.bias
                if b is None:
                    if self._empty_bias is None:
                        self._empty_bias = w.new_empty(0)
                    b = self._empty_bias
                return _conv_ext.conv2d_forward(
                    x, w, b, ph, pw, dh, dw, kh, kw, Ho, Wo)
        return self.conv2d(x)
```
Result of evaluating it:
The solution is correct on the test inputs. Mean runtime 12.3 ms; the PyTorch reference (with TF32 enabled) takes 12.3 ms; speedup 1.000x.
Profiler, top device kernels of one forward pass of your solution:
| device kernel | total device time (us) | calls |
|---|---|---|
| sm80_xmma_fprop_implicit_gemm_indexed_wo_smem_tf32f32_tf32f32_f32_nhwckrsc_nhwc_tilesize12 | 11050.7 | 1 |
| void cudnn::engines_precompiled::nhwcToNchwKernel<float, float, float, true, false, (cudnn | 758.7 | 1 |
| void cudnn::engines_precompiled::nchwToNhwcKernel<float, float, float, false, true, (cudnn | 423.4 | 2 |

The fastest correct solution so far (1.000x speedup) is:
```python
import torch
import torch.nn as nn
from torch.utils.cpp_extension import load_inline

_cuda_src = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>
#include <cstdint>

#define OH 8
#define OW 32
#define KWMAX 16
#define CDIM 32
#define SDIM (OW + 3 * (KWMAX - 1) + 1)
#define SL_FLOATS (CDIM * OH * SDIM)
#define TK (2 * SL_FLOATS)
#define WW_FLOATS (KWMAX * CDIM * 64)
#define WW_OFF TK
#define SL_ACT (CDIM * OH * (OW + 24) + 16)
#define EPI_OFF (WW_OFF + SL_ACT)
#define NTCTA 256

__device__ __forceinline__ uint32_t f2tf32(float x) {
    uint32_t r;
    asm volatile("cvt.rna.tf32.f32 %0, %1;\n" : "=r"(r) : "f"(x));
    return r;
}

__device__ __forceinline__ void mma_tf32(float &d0, float &d1, float &d2, float &d3,
                                         uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3,
                                         uint32_t b0, uint32_t b1) {
    asm volatile(
        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 "
        "{%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%0,%1,%2,%3};\n"
        : "+f"(d0), "+f"(d1), "+f"(d2), "+f"(d3)
        : "r"(a0), "r"(a1), "r"(a2), "r"(a3), "r"(b0), "r"(b1));
}

__device__ __forceinline__ uint32_t smem_u32(const void* p) {
    return (uint32_t)__cvta_generic_to_shared(p);
}

__device__ __forceinline__ void cp4(uint32_t dst, const float* src, bool pred) {
    int sz = pred ? 4 : 0;
    asm volatile("cp.async.ca.shared.global [%0], [%1], 4, %2;\n"
                 :: "r"(dst), "l"(src), "r"(sz));
}

__device__ __forceinline__ void cp_commit() { asm volatile("cp.async.commit_group;\n"); }

template <int N>
__device__ __forceinline__ void cp_wait() { asm volatile("cp.async.wait_group %0;\n" :: "n"(N)); }

__global__ void repack_round_kernel(const float* __restrict__ w, float* __restrict__ wt, int total) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < total) {
        int n = idx & 63;
        int ck = idx >> 6;
        int c = ck % CDIM;
        int t = ck / CDIM;
        int kw = (int)(w) ? 0 : 0;  // placeholder (unused)
        wt[idx] = __uint_as_float(f2tf32(w[((long)n * gridDim.y + blockIdx.y) * 1 + 0]));
    }
}

// Repack: w[n, c, i, j] -> wt[(i*kw + j)*CDIM*64 + c*64 + n], with tf32 rounding.
__global__ void repack_w_kernel(const float* __restrict__ w, float* __restrict__ wt,
                                int C, int N, int kh, int kw) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int total = kh * kw * C * N;
    if (idx < total) {
        int n = idx % N;
        int r = idx / N;
        int c = r % C;
        int t = r / C;
        int i = t / kw;
        int j = t - i * kw;
        wt[idx] = __uint_as_float(f2tf32(w[((long)n * C + c) * kh * kw + t]));
    }
}

// Main convolution kernel.
// Grid: x -> spatial tiles (th * tw), y -> batch, z -> c-half (0,1).
// Block: 256 threads (8 warps). Each CTA computes out[b, 0:64, H0:H0+8, W0:W0+32]
// for 16 input channels.
__global__ void __launch_bounds__(NTCTA)
conv2d_direct_tc_kernel(const float* __restrict__ x, const float* __restrict__ wt,
                        const float* __restrict__ bias, float* __restrict__ out,
                        int Bc, int C, int Hin, int Win, int Ho, int Wo,
                        int kh, int kw, int dh, int dw, int ph, int pw) {
    extern __shared__ float smem[];
    float* Xs = smem;                       // TK floats
    float* Ww = smem + WW_OFF;              // SL_ACT floats (reused: slice i=KHMAX-1 + bias)
    float* Ep = smem + EPI_OFF;             // 8*64 staging

    const int tid = threadIdx.x;
    const int lane = tid & 31;
    const int warp = tid >> 5;

    const int tile = blockIdx.x;
    const int tw = (Wo + OW - 1) / OW;
    const int H0 = (tile / tw) * OH;
    const int W0 = (tile - (tile / tw) * tw) * OW;
    const int b = blockIdx.y;
    const int chalf = blockIdx.z;
    const int cbase = chalf * 16;
    const int i_extent = (kh - 1) * dh;

    const int h_lim = Ho - H0 < OH ? Ho - H0 : OH;
    const int w_lim = Wo - W0 < OW ? Wo - W0 : OW;

    const int lr = lane >> 2;   // 0..7
    const int lq = lane & 3;    // 0..3

    const long HWo = (long)Ho * Wo;
    const long inHW = (long)Hin * Win;
    const float* xb = x + (long)b * C * inHW;

    // ---- slice loader: loads Xs layout [c][r][s] (tf32 rounded) ----
    auto load_slice = [&](int i, int buf) {
        int hh0 = H0 + i * dh - ph;
        int ww0 = W0 - pw;
        int ncols = OW + 3 * (kw - 1);
        int total = 16 * OH * ncols;
        float* dstb = Xs + buf * SL_FLOATS;
        for (int idx = tid; idx < total; idx += NTCTA) {
            int s = idx % ncols;
            int t2 = idx / ncols;
            int r = t2 & (OH - 1);
            int cl = t2 >> 3;
            int hh = hh0 + r;
            int ww = ww0 + s;
            bool v = ((unsigned)hh < (unsigned)Hin) && ((unsigned)ww < (unsigned)Win);
            const float* src = xb + (long)(cbase + cl) * inHW + (long)hh * Win + ww;
            float fv = 0.f;
            if (v) fv = __ldg(src);
            dstb[cl * (OH * SDIM) + r * SDIM + s] = __uint_as_float(f2tf32(fv));
        }
    };

    // ---- weight chunk loader: Ww[j*CDIM*64 + k*64 + n] = wt[((i*kw+j)*C + cbase+k)*64 + n] ----
    auto load_w = [&](int i) {
        int ncols = OW + 3 * (kw - 1);
        float* dst = Ww;
        const float* srcb = wt + ((long)i * kw * C + cbase) * 64;
        int total = kw * 16 * 64;
        for (int idx = tid; idx < total; idx += NTCTA) {
            int n = idx & 63;
            int t2 = idx >> 6;
            int k = t2 & 15;
            int j = t2 >> 4;
            dst[j * (CDIM * 64) + k * 64 + n] = __ldg(srcb + ((long)j * C + k) * 64 + n);
        }
        // zero-pad k=16..31 and round region for slice KHMAX-1
        int total2 = kw * (CDIM * 64);
        for (int idx = total + tid; idx < total2; idx += NTCTA) dst[idx] = 0.f;
        float* dst2 = Ww + WW_FLOATS;
        int total3 = 16 * OH * ncols;
        for (int idx = tid; idx < total3; idx += NTCTA) {
            int s = idx % ncols;
            int t2 = idx / ncols;
            int r = t2 & (OH - 1);
            int cl = t2 >> 3;
            dst2[cl * (OH * SDIM) + r * SDIM + s] = 0.f;
        }
    };

    // ---- accumulators ----
    float acc[2][8][4];
    #pragma unroll
    for (int mi = 0; mi < 2; ++mi)
        #pragma unroll
        for (int ni = 0; ni < 8; ++ni)
            #pragma unroll
            for (int v = 0; v < 4; ++v) acc[mi][ni][v] = 0.f;

    // precompute per-lane A source offsets
    const int m0 = warp * 32 + lr;          // m for a0/a2 (mt=0)
    const int h_r0 = m0 >> 5, w_r0 = m0 & 31;
    const int h_r1 = (m0 + 8) >> 5, w_r1 = (m0 + 8) & 31;
    const int h_r2 = (m0 + 16) >> 5, w_r2 = (m0 + 16) & 31;
    const int h_r3 = (m0 + 24) >> 5, w_r3 = (m0 + 24) & 31;

    const int nbase = lr * 2;               // n for B frag

    load_slice(0, 0);
    load_w(0);
    cp_commit();

    const int kchunks = kh;  // i-loop
    for (int i = 0; i < kchunks; ++i) {
        int buf = i & 1;
        cp_wait<0>();
        __syncthreads();
        if (i + 1 < kchunks) {
            load_slice(i + 1, buf ^ 1);
            load_w(i + 1);
            cp_commit();
        }
        const float* sl = (i == kchunks - 1) ? (Ww + WW_FLOATS) : (Xs + buf * SL_FLOATS);
        const float* wch = Ww;

        #pragma unroll 1
        for (int j = 0; j < kw; ++j) {
            const float* wj = wch + j * (CDIM * 64);
            #pragma unroll
            for (int kc = 0; kc < 2; ++kc) {
                uint32_t a[2][4];
                #pragma unroll
                for (int mt = 0; mt < 2; ++mt) {
                    const float* base0 = sl + (kc * 16 + lq) * (OH * SDIM) + 3 * j;
                    const float* base4 = sl + (kc * 16 + 4 + lq) * (OH * SDIM) + 3 * j;
                    int ro0 = mt ? h_r2 : h_r0;
                    int co0 = mt ? w_r2 : w_r0;
                    int ro1 = mt ? h_r3 : h_r1;
                    int co1 = mt ? w_r3 : w_r1;
                    a[mt][0] = __float_as_uint(base0[ro0 * SDIM + co0]);
                    a[mt][1] = __float_as_uint(base0[ro1 * SDIM + co1]);
                    a[mt][2] = __float_as_uint(base4[ro0 * SDIM + co0]);
                    a[mt][3] = __float_as_uint(base4[ro1 * SDIM + co1]);
                }
                #pragma unroll
                for (int nt = 0; nt < 8; ++nt) {
                    const float* wp = wj + (kc * 16 + lq) * 64 + nt * 8 + nbase;
                    uint32_t b0 = __float_as_uint(wp[0]);
                    uint32_t b1 = __float_as_uint(wp[256]);
                    mma_tf32(acc[0][nt][0], acc[0][nt][1], acc[0][nt][2], acc[0][nt][3],
                             a[0][0], a[0][1], a[0][2], a[0][3], b0, b1);
                    mma_tf32(acc[1][nt][0], acc[1][nt][1], acc[1][nt][2], acc[1][nt][3],
                             a[1][0], a[1][1], a[1][2], a[1][3], b0, b1);
                }
            }
        }
        if (i + 1 < kchunks) {
            // ensure all warps done reading buffers before they are reused next stage
        }
    }

    // ---- epilogue: stage through smem, coalesced NCHW store with bias ----
    // bias into Ww area (slice data no longer needed)
    if (tid < 64) Ww[tid] = bias ? bias[tid] : 0.f;
    __syncthreads();

    const int h_lo = warp >> 1;             // 0..3
    const int m_lo = warp & 1;              // 0..1
    #pragma unroll
    for (int mt = 0; mt < 2; ++mt) {
        #pragma unroll
        for (int nt = 0; nt < 8; ++nt) {
            #pragma unroll
            for (int v = 0; v < 4; ++v) {
                int mm = mt * 16 + ((v >> 1) ? 8 : 0) + lr;
                int h = mm >> 5;
                int w = mm & 31;
                int n = nt * 8 + lq * 2 + (v & 1);
                float val = acc[mt][nt][v] + Ww[n];
                Ep[((h - h_lo) & 3) * (2 * 16 * 64) + ((w >> 4) ^ m_lo) * (16 * 64) + (w & 15) * 64 + n] = val;
            }
        }
    }
    __syncthreads();

    const int r16 = tid >> 4;   // 0..15
    const int c16 = tid & 15;   // 0..15
    #pragma unroll
    for (int rep = 0; rep < 2; ++rep) {
        int rr = rep * 16 + r16;
        int h = rr >> 3;
        int w = (rr & 7) * 4 + c16;
        if (h < h_lim && w < w_lim) {
            int hs = (h - h_lo) & 3;
            const float* src = Ep + hs * (2 * 16 * 64) + ((w >> 4) ^ ((rr & 4) >> 2)) * (16 * 64) + (w & 15) * 64;
            float4* dst = reinterpret_cast<float4*>(
                out + ((long)b * 64) * HWo + (long)(H0 + h) * Wo + (W0 + w));
            const float4* s4 = reinterpret_cast<const float4*>(src);
            #pragma unroll
            for (int q = 0; q < 16; ++q) {
                dst[(long)(q * 4) * HWo] = s4[q];
            }
        }
    }
}

torch::Tensor conv2d_forward(torch::Tensor x, torch::Tensor wt, torch::Tensor bias,
                             int64_t ph, int64_t pw, int64_t dh, int64_t dw,
                             int64_t kh, int64_t kw) {
    TORCH_CHECK(x.is_cuda() && x.dtype() == torch::kFloat, "x must be CUDA fp32");
    TORCH_CHECK(x.dim() == 4 && x.size(1) == 32, "x must be NCHW with C=32");
    auto xc = x.contiguous();
    auto wc = wt.contiguous();

    const int Bc = (int)xc.size(0);
    const int C = (int)xc.size(1);
    const int Hin = (int)xc.size(2);
    const int Win = (int)xc.size(3);
    const int Ho = (Hin + 2 * (int)ph - (int)dh * ((int)kh - 1) - 1) + 1;
    const int Wo = (Win + 2 * (int)pw - (int)dw * ((int)kw - 1) - 1) + 1;

    auto out = torch::empty({Bc, 64, Ho, Wo}, xc.options());

    const int th = (Ho + OH - 1) / OH;
    const int tw = (Wo + OW - 1) / OW;
    dim3 grid(th * tw, Bc, 2);

    const int smem = (TK + SL_ACT + 8 * 64) * 4;
    static int configured_smem = 0;
    if (smem > configured_smem) {
        cudaFuncSetAttribute(conv2d_direct_tc_kernel,
                             cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
        configured_smem = smem;
    }
    const float* bias_ptr = (bias.defined() && bias.numel() > 0)
                                ? bias.data_ptr<float>() : nullptr;
    auto stream = at::cuda::getCurrentCUDAStream();
    conv2d_direct_tc_kernel<<<grid, NTCTA, smem, stream>>>(
        xc.data_ptr<float>(), wc.data_ptr<float>(), bias_ptr, out.data_ptr<float>(),
        Bc, C, Hin, Win, Ho, Wo, (int)kh, (int)kw, (int)dh, (int)dw, (int)ph, (int)pw);
    return out;
}

torch::Tensor repack_w(torch::Tensor w) {
    TORCH_CHECK(w.is_cuda() && w.dtype() == torch::kFloat && w.dim() == 4, "bad w");
    auto wc = w.contiguous();
    const int N = (int)wc.size(0);
    const int C = (int)wc.size(1);
    const int kh = (int)wc.size(2);
    const int kw = (int)wc.size(3);
    TORCH_CHECK(N == 64, "N must be 64");
    auto wt = torch::empty({(long)kh * kw * C * N}, wc.options());
    int total = kh * kw * C * N;
    int threads = 256;
    int blocks = (total + threads - 1) / threads;
    auto stream = at::cuda::getCurrentCUDAStream();
    repack_w_kernel<<<blocks, threads, 0, stream>>>(
        wc.data_ptr<float>(), wt.data_ptr<float>(), C, N, kh, kw);
    return wt;
}
"""

_cpp_src = """
torch::Tensor conv2d_forward(torch::Tensor x, torch::Tensor wt, torch::Tensor bias,
                             int64_t ph, int64_t pw, int64_t dh, int64_t dw,
                             int64_t kh, int64_t kw);
torch::Tensor repack_w(torch::Tensor w);
"""

_conv_ext = load_inline(
    name="conv2d_direct_tc_v3",
    cpp_sources=_cpp_src,
    cuda_sources=_cuda_src,
    functions=["conv2d_forward", "repack_w"],
    verbose=False,
    extra_cuda_cflags=["-O3"],
)


def _pair(v):
    if isinstance(v, int):
        return (v, v)
    return (int(v[0]), int(v[1]))


class ModelNew(nn.Module):
    def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,
                 stride: int = 1, padding: tuple = (0, 0), dilation: tuple = (1, 1),
                 bias: bool = False):
        super(ModelNew, self).__init__()
        self.conv2d = nn.Conv2d(in_channels, out_channels, kernel_size,
                                stride=stride, padding=padding,
                                dilation=dilation, bias=bias)
        self._stride = _pair(stride)
        self._padding = _pair(padding)
        self._dilation = _pair(dilation)
        self._cached_wt = None
        self._cached_version = -1
        self._fast = None
        self._empty_bias = None

    def _fast_ok(self, x):
        if self._fast is None:
            ok = False
            try:
                cap = torch.cuda.get_device_capability(x.device)
                w = self.conv2d.weight
                ok = (cap[0] >= 8 and w.shape[0] == 64 and w.shape[1] == 32
                      and w.shape[2] <= 8 and w.shape[3] <= KWMAX
                      and self._stride == (1, 1)
                      and self._dilation[0] <= 4 and self._dilation[1] <= 4)
            except Exception:
                ok = False
            self._fast = ok
        return self._fast

    def forward(self, x: torch.Tensor) -> torch.Tensor:
        w = self.conv2d.weight
        if (x.is_cuda and x.dtype == torch.float32 and w.dtype == torch.float32
                and self._fast_ok(x)):
            if (self._cached_wt is None or self._cached_version != w._version
                    or self._cached_wt.device != w.device):
                self._cached_wt = _conv_ext.repack_w(w.detach())
                self._cached_version = w._version
            b = self.conv2d.bias
            if b is None:
                if self._empty_bias is None:
                    self._empty_bias = w.new_empty(0)
                b = self._empty_bias
            return _conv_ext.conv2d_forward(
                x, self._cached_wt, b,
                self._padding[0], self._padding[1],
                self._dilation[0], self._dilation[1],
                w.shape[2], w.shape[3])
        return self.conv2d(x)
```

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.


Precision rule: the timed forward must compute in FP32 (TF32 tensor-core math is allowed, as in the PyTorch reference). Do not cast inputs, weights or intermediate results to float16 or bfloat16 and do not call half-precision kernels in forward().
