```python
import torch
import torch.nn as nn
from torch.utils.cpp_extension import load_inline

# ----------------------------------------------------------------------------
# Custom near-FP32-accurate tensor-core CUDA kernel for the dilated 2D conv
# (specialized: kernel=(5,9), stride=1, dilation=(2,3), any padding/channels).
#
# Approach: implicit-GEMM style direct convolution using fp16 tensor-core
# mma (m16n8k8) with an error-compensated hi/lo split of both operands:
#     x = x_hi + x_lo   (each fp16; combined error ~2^-22 relative)
#     a.b ~= a_hi*b_hi + a_hi*b_lo + a_lo*b_hi      (3 mmas, FP32 accumulate)
# This keeps accuracy in the same class as a plain FP32 kernel (unlike raw
# TF32/FP16), while running on the fp16 tensor cores (312 TFLOPS on A100),
# giving an effective ~104 TFLOPS of useful math -- far above the 19.5
# TFLOPS FP32 CUDA-core peak that dilated convolutions are usually stuck at.
#
# Layout choices:
#   * Block = 128 threads (4 warps); tile = 8 output rows x 16 output cols,
#     all 64 output channels of one image.  Each warp owns 2 m16-tiles
#     (one m16 tile = 16 consecutive output columns of one row, so the
#     dilation shifts become compile-time offsets per tap).
#   * Zero-padded input tile (16x40 per channel) is staged in shared memory
#     in chunks of 8 channels, pre-split and packed as half2 channel pairs
#     (hi and lo planes), with a padded stride for conflict-free A-fragment
#     gathers.
#   * Weights are transposed/split once per forward by a tiny pre-kernel
#     into [tap][ic/2][oc] half2 (hi/lo) arrays; B fragments are loaded
#     straight from global memory (L1/L2 resident, reused by every warp).
#   * 4 blocks per SM (16 warps) hide mma and global-load latency.
# ----------------------------------------------------------------------------

conv2d_cuda_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <vector>

#define KH        5
#define KW        9
#define NTAP      (KH * KW)            // 45
#define OH_TILE   8
#define OW_TILE   16
#define IN_H      (OH_TILE + (KH - 1) * 2)   // 16  (dilation h = 2)
#define IN_W      (OW_TILE + (KW - 1) * 3)   // 40  (dilation w = 3)
#define PIX       (IN_H * IN_W)              // 640
#define PLANE     648                        // padded so PLANE % 32 == 8
#define PAIRS     4                          // 8 input channels per chunk
#define SMEM_U32  (2 * PAIRS * PLANE)
#define NTHREADS  128

// ---------------------------------------------------------------------------
// Pre-kernel: transpose + split weights [OC][IC][45] ->
// hi/lo u32 (half2 channel pairs) arrays [45][ICP][OC_PAD].
// ---------------------------------------------------------------------------
__global__ void wsplit_kernel(const float* __restrict__ w,
                              unsigned* __restrict__ w_hi,
                              unsigned* __restrict__ w_lo,
                              const int IC, const int OC,
                              const int ICP, const int OCP) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    const int total = NTAP * ICP * OCP;
    if (idx >= total) return;
    const int oc = idx % OCP;
    const int t  = idx / OCP;
    const int p  = t % ICP;
    const int tap = t / ICP;
    const int ic0 = 2 * p;
    const int ic1 = ic0 + 1;

    float v0 = 0.0f, v1 = 0.0f;
    if (oc < OC) {
        if (ic0 < IC) v0 = __ldg(w + ((long)oc * IC + ic0) * NTAP + tap);
        if (ic1 < IC) v1 = __ldg(w + ((long)oc * IC + ic1) * NTAP + tap);
    }
    __half h0 = __float2half_rn(v0);
    __half h1 = __float2half_rn(v1);
    __half l0 = __float2half_rn(v0 - __half2float(h0));
    __half l1 = __float2half_rn(v1 - __half2float(h1));
    __half2 hh = __halves2half2(h0, h1);
    __half2 ll = __halves2half2(l0, l1);
    w_hi[idx] = *reinterpret_cast<unsigned*>(&hh);
    w_lo[idx] = *reinterpret_cast<unsigned*>(&ll);
}

// ---------------------------------------------------------------------------
// Main kernel.
// grid: (ceil(WO/16), ceil(HO/8), N*ceil(OC/64));  block: 128 threads.
// ---------------------------------------------------------------------------
__global__ void __launch_bounds__(NTHREADS)
conv2d_f16x3_kernel(const float* __restrict__ x,
                    const unsigned* __restrict__ w_hi,  // [45][ICP][OCP]
                    const unsigned* __restrict__ w_lo,
                    const float* __restrict__ bias,     // may be null
                    float* __restrict__ out,
                    const int N, const int IC, const int H, const int W,
                    const int OC, const int HO, const int WO,
                    const int ICP, const int OCP,
                    const int pad_h, const int pad_w) {

    __shared__ unsigned s_hi[PAIRS * PLANE];
    __shared__ unsigned s_lo[PAIRS * PLANE];

    const int tid  = threadIdx.x;
    const int warp = tid >> 5;
    const int lane = tid & 31;

    const int oc_blocks = (OC + 63) >> 6;
    const int bz  = blockIdx.z;
    const int n   = bz / oc_blocks;
    const int oc0 = (bz % oc_blocks) << 6;
    const int oh0 = blockIdx.y * OH_TILE;
    const int ow0 = blockIdx.x * OW_TILE;

    // warp -> m-tiles {warp, warp+4}; m-tile mt covers output row mt of the
    // tile and 16 consecutive output columns.
    const int rA  = warp;
    const int rB  = warp + 4;
    const int lm0 = lane >> 2;    // 0..7  (m offset within tile row)
    const int lk0 = lane & 3;     // 0..3  (channel-pair index within chunk)

    float c[2][8][4];
#pragma unroll
    for (int i = 0; i < 2; ++i)
#pragma unroll
        for (int j = 0; j < 8; ++j)
#pragma unroll
            for (int q = 0; q < 4; ++q) c[i][j][q] = 0.0f;

    const float* x_base = x + (long)n * IC * H * W;

    for (int ic0 = 0; ic0 < IC; ic0 += 2 * PAIRS) {
        const int chunk = min(2 * PAIRS, IC - ic0);
        const int cpairs = (chunk + 1) >> 1;

        // ---- Stage zero-padded input tile, split into hi/lo half2 pairs ---
        {
            const int in_r0 = oh0 - pad_h;
            const int in_c0 = ow0 - pad_w;
            for (int idx = tid; idx < cpairs * PIX; idx += NTHREADS) {
                const int p   = idx / PIX;
                const int rem = idx - p * PIX;
                const int sr  = rem / IN_W;
                const int sc  = rem - sr * IN_W;
                const int ih  = in_r0 + sr;
                const int iw  = in_c0 + sc;
                float v0 = 0.0f, v1 = 0.0f;
                if ((unsigned)ih < (unsigned)H && (unsigned)iw < (unsigned)W) {
                    const int icA = ic0 + 2 * p;
                    const int icB = icA + 1;
                    const long off = ((long)icA * H + ih) * W + iw;
                    v0 = __ldg(x_base + off);
                    v1 = (icB < IC) ? __ldg(x_base + (long)H * W + off) : 0.0f;
                }
                __half h0 = __float2half_rn(v0);
                __half h1 = __float2half_rn(v1);
                __half l0 = __float2half_rn(v0 - __half2float(h0));
                __half l1 = __float2half_rn(v1 - __half2float(h1));
                __half2 hh = __halves2half2(h0, h1);
                __half2 ll = __halves2half2(l0, l1);
                s_hi[p * PLANE + sr * IN_W + sc] = *reinterpret_cast<unsigned*>(&hh);
                s_lo[p * PLANE + sr * IN_W + sc] = *reinterpret_cast<unsigned*>(&ll);
            }
        }
        __syncthreads();

        // ---- Accumulate over the 45 taps ---------------------------------
        const int icp0 = ic0 >> 1;
#pragma unroll
        for (int kg = 0; kg < KH; ++kg) {
#pragma unroll
            for (int kw = 0; kw < KW; ++kw) {
                const int tap = kg * KW + kw;

                // A fragments (hi/lo) for the two m-tiles of this warp.
                const int paA = (rA + 2 * kg) * IN_W + 3 * kw + lm0;
                const int paB = (rB + 2 * kg) * IN_W + 3 * kw + lm0;
                const unsigned* sA_h = s_hi + lk0 * PLANE + paA;
                const unsigned* sB_h = s_hi + lk0 * PLANE + paB;
                const unsigned* sA_l = s_lo + lk0 * PLANE + paA;
                const unsigned* sB_l = s_lo + lk0 * PLANE + paB;

                unsigned a_h[2][4], a_l[2][4];
                a_h[0][0] = sA_h[0];
                a_h[0][1] = sA_h[8];
                a_h[0][2] = sA_h[2 * PLANE];
                a_h[0][3] = sA_h[2 * PLANE + 8];
                a_h[1][0] = sB_h[0];
                a_h[1][1] = sB_h[8];
                a_h[1][2] = sB_h[2 * PLANE];
                a_h[1][3] = sB_h[2 * PLANE + 8];
                a_l[0][0] = sA_l[0];
                a_l[0][1] = sA_l[8];
                a_l[0][2] = sA_l[2 * PLANE];
                a_l[0][3] = sA_l[2 * PLANE + 8];
                a_l[1][0] = sB_l[0];
                a_l[1][1] = sB_l[8];
                a_l[1][2] = sB_l[2 * PLANE];
                a_l[1][3] = sB_l[2 * PLANE + 8];

                // B fragments (hi/lo): 8 n-tiles of 8 output channels each.
                const unsigned* wr_h =
                    w_hi + ((long)tap * ICP + icp0 + lk0) * OCP + oc0 + lm0;
                const unsigned* wr_l =
                    w_lo + ((long)tap * ICP + icp0 + lk0) * OCP + oc0 + lm0;

#pragma unroll
                for (int j = 0; j < 8; ++j) {
                    const unsigned bh0 = __ldg(wr_h + j * 8);
                    const unsigned bh1 = __ldg(wr_h + j * 8 + 2 * OCP);
                    const unsigned bl0 = __ldg(wr_l + j * 8);
                    const unsigned bl1 = __ldg(wr_l + j * 8 + 2 * OCP);
#pragma unroll
                    for (int i = 0; i < 2; ++i) {
                        asm volatile(
                            "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 "
                            "{%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, "
                            "{%0,%1,%2,%3};\n"
                            : "+f"(c[i][j][0]), "+f"(c[i][j][1]),
                              "+f"(c[i][j][2]), "+f"(c[i][j][3])
                            : "r"(a_h[i][0]), "r"(a_h[i][1]),
                              "r"(a_h[i][2]), "r"(a_h[i][3]),
                              "r"(bh0), "r"(bh1));
                        asm volatile(
                            "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 "
                            "{%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, "
                            "{%0,%1,%2,%3};\n"
                            : "+f"(c[i][j][0]), "+f"(c[i][j][1]),
                              "+f"(c[i][j][2]), "+f"(c[i][j][3])
                            : "r"(a_l[i][0]), "r"(a_l[i][1]),
                              "r"(a_l[i][2]), "r"(a_l[i][3]),
                              "r"(bh0), "r"(bh1));
                        asm volatile(
                            "mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 "
                            "{%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, "
                            "{%0,%1,%2,%3};\n"
                            : "+f"(c[i][j][0]), "+f"(c[i][j][1]),
                              "+f"(c[i][j][2]), "+f"(c[i][j][3])
                            : "r"(a_h[i][0]), "r"(a_h[i][1]),
                              "r"(a_h[i][2]), "r"(a_h[i][3]),
                              "r"(bl0), "r"(bl1));
                    }
                }
            }
        }
        __syncthreads();
    }

    // ---- Epilogue: bias + store -------------------------------------------
    const bool has_bias = (bias != nullptr);
#pragma unroll
    for (int i = 0; i < 2; ++i) {
        const int r  = (i == 0) ? rA : rB;
        const int oh = oh0 + r;
        if (oh >= HO) continue;
#pragma unroll
        for (int j = 0; j < 8; ++j) {
            const int oc = oc0 + j * 8 + 2 * lk0;
            if (oc >= OC) continue;
            const bool two = (oc + 1 < OC);
            float c0 = c[i][j][0], c1 = c[i][j][1],
                  c2 = c[i][j][2], c3 = c[i][j][3];
            if (has_bias) {
                const float b0 = __ldg(bias + oc);
                c0 += b0; c2 += b0;
                if (two) {
                    const float b1 = __ldg(bias + oc + 1);
                    c1 += b1; c3 += b1;
                }
            }
            float* p = out + ((long)(n * OC + oc) * HO + oh) * WO + ow0;
            p[lm0]     = c0;
            p[lm0 + 8] = c2;
            if (two) {
                p[(long)HO * WO + lm0]     = c1;
                p[(long)HO * WO + lm0 + 8] = c3;
            }
        }
    }
}

// ---------------------------------------------------------------------------
torch::Tensor conv2d_forward(torch::Tensor x, torch::Tensor w,
                             c10::optional<torch::Tensor> bias_opt,
                             std::vector<int64_t> stride,
                             std::vector<int64_t> padding,
                             std::vector<int64_t> dilation) {
    TORCH_CHECK(x.is_cuda() && w.is_cuda(), "inputs must be CUDA tensors");
    TORCH_CHECK(x.scalar_type() == torch::kFloat32, "only float32 supported");
    TORCH_CHECK(x.dim() == 4 && w.dim() == 4, "x must be NCHW, w must be OIHW");
    TORCH_CHECK(stride[0] == 1 && stride[1] == 1, "kernel requires stride 1");
    TORCH_CHECK(dilation[0] == 2 && dilation[1] == 3,
                "kernel specialized for dilation (2,3)");
    TORCH_CHECK(w.size(2) == KH && w.size(3) == KW,
                "kernel specialized for kernel size (5,9)");

    const at::cuda::OptionalCUDAGuard device_guard(at::device_of(x));

    auto x_c = x.contiguous();
    auto w_c = w.contiguous();

    const int N  = x_c.size(0);
    const int IC = x_c.size(1);
    const int H  = x_c.size(2);
    const int W  = x_c.size(3);
    const int OC = w_c.size(0);

    const int pad_h = (int)padding[0];
    const int pad_w = (int)padding[1];

    const int HO = H + 2 * pad_h - 2 * (KH - 1);   // stride 1, dilation h 2
    const int WO = W + 2 * pad_w - 3 * (KW - 1);   // dilation w 3
    TORCH_CHECK(HO > 0 && WO > 0, "invalid output size");

    const int ICP = (IC + 1) / 2;
    const int OCP = ((OC + 63) / 64) * 64;

    auto out   = torch::empty({N, OC, HO, WO}, x_c.options());
    auto uopts = w_c.options().dtype(torch::kInt32);
    auto w_hi  = torch::empty({(long)NTAP * ICP * OCP}, uopts);
    auto w_lo  = torch::empty({(long)NTAP * ICP * OCP}, uopts);

    cudaStream_t stream = at::cuda::getCurrentCUDAStream();

    {
        int total = NTAP * ICP * OCP;
        int threads = 256;
        int blocks = (total + threads - 1) / threads;
        wsplit_kernel<<<blocks, threads, 0, stream>>>(
            w_c.data_ptr<float>(),
            reinterpret_cast<unsigned*>(w_hi.data_ptr<int>()),
            reinterpret_cast<unsigned*>(w_lo.data_ptr<int>()),
            IC, OC, ICP, OCP);
    }

    dim3 grid((WO + OW_TILE - 1) / OW_TILE,
              (HO + OH_TILE - 1) / OH_TILE,
              N * ((OC + 63) / 64));

    const bool has_bias =
        bias_opt.has_value() && bias_opt->defined() && bias_opt->numel() > 0;
    const float* bias_ptr = nullptr;
    torch::Tensor bias_c;
    if (has_bias) {
        bias_c = bias_opt->contiguous();
        bias_ptr = bias_c.data_ptr<float>();
    }

    conv2d_f16x3_kernel<<<grid, NTHREADS, 0, stream>>>(
        x_c.data_ptr<float>(),
        reinterpret_cast<const unsigned*>(w_hi.data_ptr<int>()),
        reinterpret_cast<const unsigned*>(w_lo.data_ptr<int>()),
        bias_ptr, out.data_ptr<float>(),
        N, IC, H, W, OC, HO, WO, ICP, OCP, pad_h, pad_w);

    return out;
}
"""

conv2d_cpp_source = r"""
#include <torch/extension.h>
#include <vector>
torch::Tensor conv2d_forward(torch::Tensor x, torch::Tensor w,
                             c10::optional<torch::Tensor> bias,
                             std::vector<int64_t> stride,
                             std::vector<int64_t> padding,
                             std::vector<int64_t> dilation);
"""

conv2d_ext = load_inline(
    name="conv2d_dilated_f16x3_v4",
    cpp_sources=[conv2d_cpp_source],
    cuda_sources=[conv2d_cuda_source],
    functions=["conv2d_forward"],
    verbose=False,
    extra_cuda_cflags=["-O3"],
    extra_cflags=["-O3"],
)


def _pair(v):
    if isinstance(v, (tuple, list)):
        return int(v[0]), int(v[1])
    return int(v), int(v)


class ModelNew(nn.Module):
    """
    Optimized version of Model.  Keeps an nn.Conv2d submodule so that
    initialization and state_dict are identical to the reference model, but
    computes the forward pass with a custom tensor-core CUDA kernel that
    uses error-compensated fp16 hi/lo splitting (3x mma.m16n8k8 with FP32
    accumulation) to reach far above FP32 CUDA-core throughput while keeping
    FP32-class accuracy.  Falls back to the standard cuDNN implementation
    for any configuration the kernel is not specialized for.
    """

    def __init__(self, in_channels: int, out_channels: int, kernel_size: tuple,
                 stride: int = 1, padding: tuple = (0, 0),
                 dilation: tuple = (1, 1), bias: bool = False):
        super(ModelNew, self).__init__()
        self.conv2d = nn.Conv2d(in_channels, out_channels, kernel_size,
                                stride=stride, padding=padding,
                                dilation=dilation, bias=bias)

        k = _pair(kernel_size)
        s = _pair(stride)
        p = _pair(padding)
        d = _pair(dilation)

        self._stride = [s[0], s[1]]
        self._padding = [p[0], p[1]]
        self._dilation = [d[0], d[1]]
        self._use_custom = (k == (5, 9) and s == (1, 1) and d == (2, 3))

    def forward(self, x: torch.Tensor) -> torch.Tensor:
        if (self._use_custom and x.is_cuda and x.dtype == torch.float32
                and x.dim() == 4):
            return conv2d_ext.conv2d_forward(
                x, self.conv2d.weight, self.conv2d.bias,
                self._stride, self._padding, self._dilation)
        return self.conv2d(x)
```