You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Simple model that performs a 3D convolution, applies minimum operation along a specific dimension, 
    and then applies softmax.
    """
    def __init__(self, in_channels, out_channels, kernel_size, dim):
        super(Model, self).__init__()
        self.conv = nn.Conv3d(in_channels, out_channels, kernel_size)
        self.dim = dim

    def forward(self, x):
        """
        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, in_channels, D, H, W)
        Returns:
            torch.Tensor: Output tensor of shape (batch_size, out_channels, H, W)
        """
        x = self.conv(x)
        x = torch.min(x, dim=self.dim)[0]  # Apply minimum along the specified dimension
        x = torch.softmax(x, dim=1)  # Apply softmax along the channel dimension
        return x

batch_size = 128
in_channels = 3
out_channels = 24  # Increased output channels
D, H, W = 24, 32, 32  # Increased depth
kernel_size = 3
dim = 2  # Dimension along which to apply minimum operation (e.g., depth)

def get_inputs():
    return [torch.rand(batch_size, in_channels, D, H, W)]

def get_init_inputs():
    return [in_channels, out_channels, kernel_size, dim]
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 5 of 6 for this task. Your previous solution (turn 4) was:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Enable cuDNN autotuning (exhaustive) so the 3D convolution picks the fastest
# available algorithm for the fixed shapes used by this model, and allow TF32
# tensor-core execution (same numerics mode as the reference configuration).
torch.backends.cudnn.benchmark = True
torch.backends.cudnn.allow_tf32 = True
torch.backends.cuda.matmul.allow_tf32 = True
try:
    torch.backends.cudnn.benchmark_limit = 0  # exhaustive autotuning
except Exception:
    pass

# Custom CUDA kernels:
#   1) nchw_to_nhwc_cuda: fully-vectorized (float4 on both sides) NCHW -> NHWC
#      transpose so cuDNN can run its NHWC kernels end-to-end.
#   2) fused_min_softmax_*_cuda: fused min-over-depth (dim=2) + per-channel
#      bias-add + softmax-over-channels (dim=1).
#
# Key algorithmic point: the conv bias is constant per output channel, so
#   min_d(conv[n,c,d,h,w] + bias[c]) == min_d(conv[n,c,d,h,w]) + bias[c]
# exactly in IEEE arithmetic (addition is monotone). We therefore call cuDNN
# WITHOUT bias -- eliminating the full-output (243 MB read + 243 MB write)
# elementwise bias-add kernel that ATen/cuDNN otherwise runs -- and fold the
# bias into the fused epilogue for free (values already live in registers).
_fused_cuda_src = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAException.h>
#include <cuda_runtime.h>
#include <cmath>
#include <cstdint>

namespace {

// ---------------------------------------------------------------------------
// NCHW -> NHWC transpose. Each thread moves 4 consecutive spatial positions
// for all channels; both loads and stores use float4 whenever alignment
// permits, and are fully coalesced across the warp.
// in:  (N, C, DS) contiguous
// out: (N, C, DS) channels_last, i.e. (N, DS, C) contiguous
// ---------------------------------------------------------------------------
template <int C>
__global__ __launch_bounds__(256) void nchw_to_nhwc_kernel(
        const float* __restrict__ in,
        float* __restrict__ out,
        int DS) {
    const int n = blockIdx.x;
    const int s0 = (blockIdx.y * blockDim.x + threadIdx.x) * 4;
    if (s0 >= DS) return;

    const float* in_n = in + (size_t)n * (size_t)C * (size_t)DS;
    float* out_n = out + (size_t)n * (size_t)DS * (size_t)C;

    if (s0 + 4 <= DS) {
        float v[C][4];
        if ((DS & 3) == 0) {
            #pragma unroll
            for (int c = 0; c < C; ++c) {
                const float4 t = *reinterpret_cast<const float4*>(
                    in_n + (size_t)c * (size_t)DS + s0);
                v[c][0] = t.x;
                v[c][1] = t.y;
                v[c][2] = t.z;
                v[c][3] = t.w;
            }
        } else {
            #pragma unroll
            for (int c = 0; c < C; ++c) {
                #pragma unroll
                for (int j = 0; j < 4; ++j) {
                    v[c][j] = in_n[(size_t)c * (size_t)DS + s0 + j];
                }
            }
        }
        if (((DS * C) & 3) == 0) {
            float4* o = reinterpret_cast<float4*>(out_n + (size_t)s0 * C);
            #pragma unroll
            for (int k = 0; k < C; ++k) {
                float4 t;
                t.x = v[(4 * k + 0) % C][(4 * k + 0) / C];
                t.y = v[(4 * k + 1) % C][(4 * k + 1) / C];
                t.z = v[(4 * k + 2) % C][(4 * k + 2) / C];
                t.w = v[(4 * k + 3) % C][(4 * k + 3) / C];
                o[k] = t;
            }
        } else {
            #pragma unroll
            for (int j = 0; j < 4; ++j) {
                #pragma unroll
                for (int c = 0; c < C; ++c) {
                    out_n[(size_t)(s0 + j) * C + c] = v[c][j];
                }
            }
        }
    } else {
        for (int s = s0; s < DS; ++s) {
            #pragma unroll
            for (int c = 0; c < C; ++c) {
                out_n[(size_t)s * C + c] = in_n[(size_t)c * (size_t)DS + s];
            }
        }
    }
}

// ---------------------------------------------------------------------------
// NHWC (channels_last_3d) fused min-over-depth + bias + softmax-over-channels.
// One thread per (n, h, w) spatial location. The per-channel values live in
// registers (C is a compile-time constant). Loads are 128-bit (float4) since
// the C channel values are contiguous in NHWC; stores are coalesced across
// the warp because consecutive threads handle consecutive spatial positions.
// ---------------------------------------------------------------------------
template <int C>
__global__ __launch_bounds__(256) void fused_min_softmax_nhwc_kernel(
        const float* __restrict__ in,
        const float* __restrict__ bias,
        float* __restrict__ out,
        int N, int D, int HW) {
    constexpr int C4 = C / 4;
    const int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx >= N * HW) return;

    const int n = idx / HW;
    const int s = idx - n * HW;

    const float4* base = reinterpret_cast<const float4*>(in)
                       + ((size_t)n * (size_t)D * (size_t)HW + (size_t)s) * C4;
    const size_t dstride = (size_t)HW * C4;

    float m[C];
    {
        const float4* p = base;
        #pragma unroll
        for (int i = 0; i < C4; ++i) {
            const float4 v = __ldcs(p + i);
            m[4 * i + 0] = v.x;
            m[4 * i + 1] = v.y;
            m[4 * i + 2] = v.z;
            m[4 * i + 3] = v.w;
        }
    }
    for (int d = 1; d < D; ++d) {
        const float4* p = base + (size_t)d * dstride;
        #pragma unroll
        for (int i = 0; i < C4; ++i) {
            const float4 v = __ldcs(p + i);
            m[4 * i + 0] = fminf(m[4 * i + 0], v.x);
            m[4 * i + 1] = fminf(m[4 * i + 1], v.y);
            m[4 * i + 2] = fminf(m[4 * i + 2], v.z);
            m[4 * i + 3] = fminf(m[4 * i + 3], v.w);
        }
    }

    // fold the per-channel conv bias in (exactly equal to adding it pre-min)
    if (bias != nullptr) {
        #pragma unroll
        for (int c = 0; c < C; ++c) m[c] += __ldg(bias + c);
    }

    // numerically stable softmax over the channel values held in registers
    float maxv = m[0];
    #pragma unroll
    for (int c = 1; c < C; ++c) maxv = fmaxf(maxv, m[c]);

    float sum = 0.0f;
    #pragma unroll
    for (int c = 0; c < C; ++c) {
        m[c] = expf(m[c] - maxv);
        sum += m[c];
    }
    const float inv = 1.0f / sum;

    float* op = out + (size_t)n * C * HW + s;
    #pragma unroll
    for (int c = 0; c < C; ++c) {
        op[(size_t)c * HW] = m[c] * inv;
    }
}

// Generic NHWC fallback for arbitrary channel counts: one block per (n, h, w),
// threads cooperate over channels using shared memory.
__global__ void fused_min_softmax_nhwc_generic_kernel(
        const float* __restrict__ in,
        const float* __restrict__ bias,
        float* __restrict__ out,
        int N, int C, int D, int HW) {
    extern __shared__ float smem[];  // [0..C): per-channel mins/exps, then reduction scratch
    const int n = blockIdx.x / HW;
    const int s = blockIdx.x - n * HW;
    const int tid = threadIdx.x;
    const int nt = blockDim.x;

    const float* base = in + ((size_t)n * (size_t)D * (size_t)HW + (size_t)s) * (size_t)C;
    const size_t dstride = (size_t)HW * (size_t)C;

    for (int c = tid; c < C; c += nt) {
        float m = base[c];
        for (int d = 1; d < D; ++d) m = fminf(m, base[(size_t)d * dstride + c]);
        if (bias != nullptr) m += __ldg(bias + c);
        smem[c] = m;
    }
    __syncthreads();

    float* red = smem + C;
    float lmax = -INFINITY;
    for (int c = tid; c < C; c += nt) lmax = fmaxf(lmax, smem[c]);
    red[tid] = lmax;
    __syncthreads();
    for (int st = nt >> 1; st > 0; st >>= 1) {
        if (tid < st) red[tid] = fmaxf(red[tid], red[tid + st]);
        __syncthreads();
    }
    const float maxv = red[0];
    __syncthreads();

    float lsum = 0.0f;
    for (int c = tid; c < C; c += nt) {
        const float e = expf(smem[c] - maxv);
        smem[c] = e;
        lsum += e;
    }
    red[tid] = lsum;
    __syncthreads();
    for (int st = nt >> 1; st > 0; st >>= 1) {
        if (tid < st) red[tid] += red[tid + st];
        __syncthreads();
    }
    const float inv = 1.0f / red[0];

    float* op = out + (size_t)n * (size_t)C * (size_t)HW + s;
    for (int c = tid; c < C; c += nt) {
        op[(size_t)c * HW] = smem[c] * inv;
    }
}

// ---------------------------------------------------------------------------
// NCHW (contiguous) fused min-over-depth + bias + softmax-over-channels
// (fallback). One thread per (n, h, w) spatial location; per-channel values
// in registers. All loads/stores are coalesced across the warp.
// ---------------------------------------------------------------------------
template <int C>
__global__ void fused_min_softmax_nchw_kernel(
        const float* __restrict__ in,
        const float* __restrict__ bias,
        float* __restrict__ out,
        int N, int D, int HW) {
    const int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx >= N * HW) return;

    const int n = idx / HW;
    const int s = idx - n * HW;

    const float* in_n = in + (size_t)n * C * D * HW + s;

    float vals[C];
    #pragma unroll
    for (int c = 0; c < C; ++c) {
        const float* p = in_n + (size_t)c * D * HW;
        float m = p[0];
        #pragma unroll 4
        for (int d = 1; d < D; ++d) {
            m = fminf(m, p[(size_t)d * HW]);
        }
        if (bias != nullptr) m += __ldg(bias + c);
        vals[c] = m;
    }

    float maxv = vals[0];
    #pragma unroll
    for (int c = 1; c < C; ++c) maxv = fmaxf(maxv, vals[c]);

    float sum = 0.0f;
    #pragma unroll
    for (int c = 0; c < C; ++c) {
        vals[c] = expf(vals[c] - maxv);
        sum += vals[c];
    }
    const float inv = 1.0f / sum;

    float* out_n = out + (size_t)n * C * HW + s;
    #pragma unroll
    for (int c = 0; c < C; ++c) {
        out_n[(size_t)c * HW] = vals[c] * inv;
    }
}

__global__ void fused_min_softmax_nchw_generic_kernel(
        const float* __restrict__ in,
        const float* __restrict__ bias,
        float* __restrict__ out,
        int N, int C, int D, int HW) {
    extern __shared__ float smem[];
    const int n = blockIdx.x / HW;
    const int s = blockIdx.x - n * HW;
    const int tid = threadIdx.x;
    const int nt = blockDim.x;

    const float* in_n = in + (size_t)n * C * D * HW + s;

    for (int c = tid; c < C; c += nt) {
        const float* p = in_n + (size_t)c * D * HW;
        float m = p[0];
        for (int d = 1; d < D; ++d) m = fminf(m, p[(size_t)d * HW]);
        if (bias != nullptr) m += __ldg(bias + c);
        smem[c] = m;
    }
    __syncthreads();

    float* red = smem + C;
    float lmax = -INFINITY;
    for (int c = tid; c < C; c += nt) lmax = fmaxf(lmax, smem[c]);
    red[tid] = lmax;
    __syncthreads();
    for (int st = nt >> 1; st > 0; st >>= 1) {
        if (tid < st) red[tid] = fmaxf(red[tid], red[tid + st]);
        __syncthreads();
    }
    const float maxv = red[0];
    __syncthreads();

    float lsum = 0.0f;
    for (int c = tid; c < C; c += nt) {
        const float e = expf(smem[c] - maxv);
        smem[c] = e;
        lsum += e;
    }
    red[tid] = lsum;
    __syncthreads();
    for (int st = nt >> 1; st > 0; st >>= 1) {
        if (tid < st) red[tid] += red[tid + st];
        __syncthreads();
    }
    const float inv = 1.0f / red[0];

    float* out_n = out + (size_t)n * C * HW + s;
    for (int c = tid; c < C; c += nt) {
        out_n[(size_t)c * HW] = smem[c] * inv;
    }
}

const float* get_bias_ptr(const c10::optional<torch::Tensor>& bias_opt, int C) {
    if (!bias_opt.has_value() || !bias_opt->defined()) return nullptr;
    const auto& b = *bias_opt;
    TORCH_CHECK(b.is_cuda(), "bias must be a CUDA tensor");
    TORCH_CHECK(b.scalar_type() == at::kFloat, "bias must be float32");
    TORCH_CHECK(b.numel() >= C, "bias must have at least C elements");
    TORCH_CHECK(b.is_contiguous(), "bias must be contiguous");
    return b.data_ptr<float>();
}

}  // namespace

torch::Tensor nchw_to_nhwc_cuda(torch::Tensor x) {
    TORCH_CHECK(x.is_cuda(), "input must be a CUDA tensor");
    TORCH_CHECK(x.dim() == 5, "input must be 5D (N, C, D, H, W)");
    TORCH_CHECK(x.scalar_type() == at::kFloat, "input must be float32");
    TORCH_CHECK(x.is_contiguous(), "input must be NCHW contiguous");

    const int N = (int)x.size(0);
    const int C = (int)x.size(1);
    const int D = (int)x.size(2);
    const int H = (int)x.size(3);
    const int W = (int)x.size(4);
    TORCH_CHECK(C >= 1 && C <= 4, "channel count must be in [1, 4]");

    auto out = at::empty({N, C, D, H, W},
                         x.options().memory_format(at::MemoryFormat::ChannelsLast3d));
    const long long DS = (long long)D * H * W;
    if (DS == 0 || N == 0) return out;

    const long long blocks_y = (DS + 256 * 4 - 1) / (256 * 4);
    TORCH_CHECK(blocks_y <= 65535, "spatial size too large for transpose kernel");

    cudaStream_t stream = at::cuda::getCurrentCUDAStream();
    const dim3 grid(N, (unsigned)blocks_y);
    const float* in_ptr = x.data_ptr<float>();
    float* out_ptr = out.data_ptr<float>();

    switch (C) {
        case 1:
            nchw_to_nhwc_kernel<1><<<grid, 256, 0, stream>>>(in_ptr, out_ptr, (int)DS);
            break;
        case 2:
            nchw_to_nhwc_kernel<2><<<grid, 256, 0, stream>>>(in_ptr, out_ptr, (int)DS);
            break;
        case 3:
            nchw_to_nhwc_kernel<3><<<grid, 256, 0, stream>>>(in_ptr, out_ptr, (int)DS);
            break;
        default:
            nchw_to_nhwc_kernel<4><<<grid, 256, 0, stream>>>(in_ptr, out_ptr, (int)DS);
            break;
    }
    C10_CUDA_KERNEL_LAUNCH_CHECK();
    return out;
}

torch::Tensor fused_min_softmax_nhwc_cuda(torch::Tensor input,
                                          c10::optional<torch::Tensor> bias) {
    TORCH_CHECK(input.is_cuda(), "input must be a CUDA tensor");
    TORCH_CHECK(input.dim() == 5, "input must be 5D (N, C, D, H, W)");
    TORCH_CHECK(input.scalar_type() == at::kFloat, "input must be float32");
    TORCH_CHECK(input.is_contiguous(at::MemoryFormat::ChannelsLast3d),
                "input must be channels_last_3d contiguous");

    const int N = (int)input.size(0);
    const int C = (int)input.size(1);
    const int D = (int)input.size(2);
    const int H = (int)input.size(3);
    const int W = (int)input.size(4);
    TORCH_CHECK(D >= 1, "depth must be >= 1");

    auto out = at::empty({N, C, H, W}, input.options());
    const int HW = H * W;
    const long long total = (long long)N * HW;
    if (total == 0 || C == 0) return out;

    cudaStream_t stream = at::cuda::getCurrentCUDAStream();
    const float* in_ptr = input.data_ptr<float>();
    const float* bias_ptr = get_bias_ptr(bias, C);
    float* out_ptr = out.data_ptr<float>();

    const bool aligned16 = ((reinterpret_cast<uintptr_t>(in_ptr)) & 0xF) == 0;
    const int threads = 256;
    const int blocks = (int)((total + threads - 1) / threads);

    bool launched = false;
    if (aligned16 && (C % 4) == 0) {
        #define FUSED_NHWC_CASE(CC)                                                \
            case CC:                                                               \
                fused_min_softmax_nhwc_kernel<CC><<<blocks, threads, 0, stream>>>( \
                    in_ptr, bias_ptr, out_ptr, N, D, HW);                          \
                launched = true;                                                   \
                break;
        switch (C) {
            FUSED_NHWC_CASE(4)
            FUSED_NHWC_CASE(8)
            FUSED_NHWC_CASE(12)
            FUSED_NHWC_CASE(16)
            FUSED_NHWC_CASE(20)
            FUSED_NHWC_CASE(24)
            FUSED_NHWC_CASE(28)
            FUSED_NHWC_CASE(32)
            FUSED_NHWC_CASE(48)
            FUSED_NHWC_CASE(64)
            FUSED_NHWC_CASE(96)
            FUSED_NHWC_CASE(128)
            default:
                break;
        }
        #undef FUSED_NHWC_CASE
    }
    if (!launched) {
        TORCH_CHECK(C <= 8192, "channel count too large for generic kernel");
        const int gthreads = 128;
        const size_t shmem = ((size_t)C + (size_t)gthreads) * sizeof(float);
        fused_min_softmax_nhwc_generic_kernel<<<(int)total, gthreads, shmem, stream>>>(
            in_ptr, bias_ptr, out_ptr, N, C, D, HW);
    }

    C10_CUDA_KERNEL_LAUNCH_CHECK();
    return out;
}

torch::Tensor fused_min_softmax_cuda(torch::Tensor input,
                                     c10::optional<torch::Tensor> bias) {
    TORCH_CHECK(input.is_cuda(), "input must be a CUDA tensor");
    TORCH_CHECK(input.dim() == 5, "input must be 5D (N, C, D, H, W)");
    TORCH_CHECK(input.scalar_type() == at::kFloat, "input must be float32");

    auto in = input.contiguous();
    const int N = (int)in.size(0);
    const int C = (int)in.size(1);
    const int D = (int)in.size(2);
    const int H = (int)in.size(3);
    const int W = (int)in.size(4);
    TORCH_CHECK(D >= 1, "depth must be >= 1");

    auto out = at::empty({N, C, H, W}, in.options());
    const int HW = H * W;
    const long long total = (long long)N * HW;
    if (total == 0 || C == 0) return out;

    cudaStream_t stream = at::cuda::getCurrentCUDAStream();
    const float* in_ptr = in.data_ptr<float>();
    const float* bias_ptr = get_bias_ptr(bias, C);
    float* out_ptr = out.data_ptr<float>();

    const int threads = 256;
    const int blocks = (int)((total + threads - 1) / threads);

    bool launched = false;
    #define FUSED_NCHW_CASE(CC)                                                  \
        case CC:                                                                 \
            fused_min_softmax_nchw_kernel<CC><<<blocks, threads, 0, stream>>>(   \
                in_ptr, bias_ptr, out_ptr, N, D, HW);                            \
            launched = true;                                                     \
            break;
    switch (C) {
        FUSED_NCHW_CASE(1)
        FUSED_NCHW_CASE(2)
        FUSED_NCHW_CASE(3)
        FUSED_NCHW_CASE(4)
        FUSED_NCHW_CASE(6)
        FUSED_NCHW_CASE(8)
        FUSED_NCHW_CASE(12)
        FUSED_NCHW_CASE(16)
        FUSED_NCHW_CASE(24)
        FUSED_NCHW_CASE(32)
        FUSED_NCHW_CASE(48)
        FUSED_NCHW_CASE(64)
        FUSED_NCHW_CASE(96)
        FUSED_NCHW_CASE(128)
        default:
            break;
    }
    #undef FUSED_NCHW_CASE
    if (!launched) {
        TORCH_CHECK(C <= 8192, "channel count too large for generic kernel");
        const int gthreads = 128;
        const size_t shmem = ((size_t)C + (size_t)gthreads) * sizeof(float);
        fused_min_softmax_nchw_generic_kernel<<<(int)total, gthreads, shmem, stream>>>(
            in_ptr, bias_ptr, out_ptr, N, C, D, HW);
    }

    C10_CUDA_KERNEL_LAUNCH_CHECK();
    return out;
}
"""

_fused_cpp_src = (
    "torch::Tensor nchw_to_nhwc_cuda(torch::Tensor x);\n"
    "torch::Tensor fused_min_softmax_nhwc_cuda(torch::Tensor input, c10::optional<torch::Tensor> bias);\n"
    "torch::Tensor fused_min_softmax_cuda(torch::Tensor input, c10::optional<torch::Tensor> bias);"
)

_ext = load_inline(
    name="fused_conv_min_softmax_ext_v4",
    cpp_sources=_fused_cpp_src,
    cuda_sources=_fused_cuda_src,
    functions=[
        "nchw_to_nhwc_cuda",
        "fused_min_softmax_nhwc_cuda",
        "fused_min_softmax_cuda",
    ],
    verbose=False,
    extra_cflags=["-O3"],
    extra_cuda_cflags=["-O3"],
)


class ModelNew(nn.Module):
    """
    Optimized version of Model:
      - The input is transposed once to channels_last_3d with a custom
        fully-vectorized CUDA kernel so cuDNN runs its NHWC kernels
        end-to-end (no NCHW<->NHWC conversion kernels inside the conv).
      - The conv weight is cached in channels_last_3d layout so cuDNN does
        not re-transform the filter on every call.
      - The convolution is launched WITHOUT bias: since the bias is constant
        per output channel, min_d(y + b) == min_d(y) + b exactly, so the bias
        is folded into the fused epilogue. This eliminates the full-output
        elementwise bias-add kernel (~360 us) entirely.
      - min-over-depth (dim=2), bias-add and softmax-over-channels (dim=1)
        are fused into a single custom CUDA kernel that reads the NHWC conv
        output directly with streaming float4 loads, keeping all per-channel
        values in registers and never materializing the intermediate tensors.
    """
    def __init__(self, in_channels, out_channels, kernel_size, dim):
        super(ModelNew, self).__init__()
        self.conv = nn.Conv3d(in_channels, out_channels, kernel_size)
        self.dim = dim
        self._w_cl = None
        self._w_src = None
        self._w_ver = -1

    def _cl_weight(self):
        w = self.conv.weight
        if (self._w_cl is None or self._w_src is not w
                or self._w_ver != w._version or self._w_cl.device != w.device):
            self._w_cl = w.detach().contiguous(
                memory_format=torch.channels_last_3d)
            self._w_src = w
            self._w_ver = w._version
        return self._w_cl

    def forward(self, x):
        """
        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, in_channels, D, H, W)
        Returns:
            torch.Tensor: Output tensor of shape (batch_size, out_channels, H, W)
        """
        dim = self.dim if self.dim >= 0 else self.dim + x.dim()
        fast = (dim == 2 and x.is_cuda and x.dtype == torch.float32)
        if not fast:
            x = self.conv(x)
            x = torch.min(x, dim=dim)[0]
            x = torch.softmax(x, dim=1)
            return x

        conv = self.conv
        # channels_last input for the NHWC conv
        if x.is_contiguous(memory_format=torch.channels_last_3d):
            x_cl = x
        elif (x.is_contiguous() and 1 <= x.size(1) <= 4
                and x.size(2) * x.size(3) * x.size(4) <= 65535 * 1024):
            x_cl = _ext.nchw_to_nhwc_cuda(x)
        else:
            x_cl = x.contiguous(memory_format=torch.channels_last_3d)

        w = conv.weight
        if not (torch.is_grad_enabled() and w.requires_grad):
            w = self._cl_weight()

        # no bias here: it is folded (exactly) into the fused epilogue
        y = F.conv3d(x_cl, w, None, conv.stride, conv.padding,
                     conv.dilation, conv.groups)

        if y.is_contiguous(memory_format=torch.channels_last_3d):
            return _ext.fused_min_softmax_nhwc_cuda(y, conv.bias)
        return _ext.fused_min_softmax_cuda(y, conv.bias)
```
Result of evaluating it:
The solution is correct on the test inputs. Mean runtime 1.02 ms; the PyTorch reference (with TF32 enabled) takes 2.06 ms; speedup 2.020x.
Profiler, top device kernels of one forward pass of your solution:
| device kernel | total device time (us) | calls |
|---|---|---|
| sm80_xmma_fprop_implicit_gemm_indexed_wo_smem_tf32f32_tf32f32_f32_nhwckrsc_nhwc_tilesize12 | 531.9 | 1 |
| void (anonymous namespace)::fused_min_softmax_nhwc_kernel<24>(float const*, float const*,  | 329.8 | 1 |
| void (anonymous namespace)::nchw_to_nhwc_kernel<3>(float const*, float*, int) | 71.3 | 1 |
| void cudnn::engines_precompiled::convertTensor_kernel<float, float, float, (cudnnKernelDat | 65.1 | 2 |
| void at::native::elementwise_kernel<128, 2, at::native::gpu_kernel_impl_nocast<at::native: | 3.6 | 1 |

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.
