You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Model that performs a transposed convolution, subtracts a bias term, and applies tanh activation.
    """
    def __init__(self, in_channels, out_channels, kernel_size, bias_shape, stride=2, padding=1, output_padding=1):
        super(Model, self).__init__()
        self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)
        self.bias = nn.Parameter(torch.randn(bias_shape)) 

    def forward(self, x):
        x = self.conv_transpose(x)
        x = x - self.bias
        x = torch.tanh(x)
        return x

batch_size = 32
in_channels  = 64  
out_channels = 64  
height = width = 256 
kernel_size = 4
bias_shape = (out_channels, 1, 1)

def get_inputs():
    return [torch.rand(batch_size, in_channels, height, width)]

def get_init_inputs():
    return [in_channels, out_channels, kernel_size, bias_shape]
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 4 of 6 for this task. Your previous solution (turn 3) was:
```python
import torch
import torch.nn as nn
from torch.utils.cpp_extension import load_inline

torch.backends.cudnn.benchmark = True
torch.backends.cudnn.allow_tf32 = True

# Custom fully-fused implementation of ConvTranspose2d(k=4,s=2,p=1,op=1)
# followed by bias-subtraction and tanh, for C_in=C_out=64, H=W=256.
#
# Pipeline:
#   1) nchw_to_nhwc_pad_kernel: converts the NCHW input into a zero-padded
#      NHWC buffer [N][258][290][64] (row pad 1 each side, col pad 1 left /
#      33 right) so the GEMM kernel can read 16-wide fragments without any
#      bounds checks.
#   2) tconv_gemm_kernel: an implicit-GEMM transposed convolution using
#      TF32 tensor cores (wmma 16x16x8). Each output pixel is a dot product
#      of a 2x2x64 input window with a 256x64 weight matrix. Weights are
#      pre-swizzled per output parity into [4][256][64] matrices.
#      Bias-subtraction and tanh are fused into the epilogue.
#      Output is written directly in NHWC (channels_last).
#
# All arguments are compile-time constants via templates so every index
# expression collapses to immediates.

custom_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>
#include <mma.h>
#include <cstdint>

using namespace nvcuda;

#define DEVINL __device__ __forceinline__

// ---------------------------------------------------------------------------
// NCHW -> padded NHWC conversion (with zero border)
// xp: [N][RP][CP][C], RP = H+2, CP = W + CPAD_TOTAL
// ---------------------------------------------------------------------------
template <int C, int H, int W, int RP, int CP>
__global__ void __launch_bounds__(256)
nchw_to_nhwc_pad_kernel(const float* __restrict__ x,
                        float* __restrict__ xp,
                        const int n_batch) {
    __shared__ float sh[C][W + 8];
    const int n  = blockIdx.x;
    const int rp = blockIdx.y;           // 0 .. RP-1
    const int tid = threadIdx.x;

    float* __restrict__ orow = xp + (((long long)n * RP + rp) * CP) * C;

    if (rp == 0 || rp == RP - 1) {
        // zero border row
        float4* o4 = reinterpret_cast<float4*>(orow);
        const int total4 = CP * (C / 4);
        const float4 z = make_float4(0.f, 0.f, 0.f, 0.f);
        for (int i = tid; i < total4; i += 256) o4[i] = z;
        return;
    }

    const int r = rp - 1;                // input row
    const float* __restrict__ xr = x + (((long long)n * C) * H + r) * W;

    // coalesced loads: 8 channels per pass
    #pragma unroll
    for (int c0 = 0; c0 < C; c0 += 8) {
        const float* src = xr + (long long)(c0) * (H * W);
        #pragma unroll
        for (int i = 0; i < 8; ++i)
            sh[c0 + i][tid] = src[(long long)i * (H * W) + tid];
    }
    __syncthreads();

    // zero left border column
    if (tid < C) orow[tid] = 0.f;

    // main body: 4 columns per pass, 64 channels each
    #pragma unroll
    for (int c0 = 0; c0 < W; c0 += 4) {
        const int cc = c0 + (tid >> 6);      // column within pass
        const int ci = tid & 63;             // channel
        orow[(cc + 1) * C + ci] = sh[ci][cc];
    }

    // zero right border columns
    const int NB = CP - 1 - W;
    if (tid < NB * C) {
        const int j = tid / C;
        const int ci = tid - j * C;
        orow[(W + 1 + j) * C + ci] = 0.f;
    }
}

// ---------------------------------------------------------------------------
// Fused transposed-conv GEMM (TF32 tensor cores) + bias-sub + tanh
// out[n, y, x, co] = tanh( sum_{t,ci} xp[n, rp, cp, ci] * W[p, t*64+ci, co]
//                          - bias[co] )
// One block: 8 same-parity output rows x 32 same-parity output cols.
// One warp: 1 output row x 32 cols  -> 2x4 fragments of 16x16.
// ---------------------------------------------------------------------------
template <int C, int HIN, int RP, int CP, int HOUT>
__global__ void __launch_bounds__(256)
tconv_gemm_kernel(const float* __restrict__ xp,
                  const float* __restrict__ wq,     // [4][4C][C]
                  const float* __restrict__ bias,   // [C]
                  float* __restrict__ out) {
    constexpr int K = 4 * C;      // reduction depth
    const int p  = blockIdx.z & 3;
    const int n  = blockIdx.z >> 2;
    const int py = p >> 1;
    const int px = p & 1;
    const int Oy = (HOUT + 1 - py) >> 1;
    const int Ox = (HOUT + 1 - px) >> 1;

    const int oby = blockIdx.y * 8;
    const int obx = blockIdx.x * 32;
    const int warp = threadIdx.x >> 5;
    const int lane = threadIdx.x & 31;

    const int orow = oby + warp;
    if (orow >= Oy) return;
    const int y = 2 * orow + py;

    wmma::fragment<wmma::accumulator, 16, 16, 8, float> acc[2][4];
    #pragma unroll
    for (int i = 0; i < 2; ++i)
        #pragma unroll
        for (int j = 0; j < 4; ++j)
            wmma::fill_fragment(acc[i][j], 0.0f);

    const float* __restrict__ wp = wq + (long long)p * (K * C);
    const long long nrow = ((long long)n * RP + orow + py) * CP + obx + px;

    #pragma unroll
    for (int t = 0; t < 4; ++t) {
        const long long abase = (nrow + (t >> 1) * CP + (t & 1)) * C;
        #pragma unroll
        for (int c0 = 0; c0 < C; c0 += 8) {
            wmma::fragment<wmma::matrix_a, 16, 16, 8,
                           wmma::precision::tf32, wmma::row_major> a[2];
            wmma::load_matrix_sync(a[0], xp + abase + c0, C);
            wmma::load_matrix_sync(a[1], xp + abase + c0 + 16 * C, C);
            const float* wptr = wp + (t * C + c0) * C;
            #pragma unroll
            for (int j = 0; j < 4; ++j) {
                wmma::fragment<wmma::matrix_b, 16, 16, 8,
                               wmma::precision::tf32, wmma::row_major> b;
                wmma::load_matrix_sync(b, wptr + j * 16, C);
                wmma::mma_sync(acc[0][j], a[0], b, acc[0][j]);
                wmma::mma_sync(acc[1][j], a[1], b, acc[1][j]);
            }
        }
    }

    // epilogue: fused bias-subtraction + tanh, direct NHWC stores
    const int g  = lane >> 2;
    const int tg = lane & 3;
    float* __restrict__ obase = out + (((long long)n * HOUT + y) * HOUT) * C;
    #pragma unroll
    for (int i = 0; i < 2; ++i) {
        const int xl0 = obx + 16 * i + g;        // logical ocol for rows g
        const int xl1 = xl0 + 8;                 // logical ocol for rows g+8
        const bool v0 = xl0 < Ox;
        const bool v1 = xl1 < Ox;
        if (!(v0 || v1)) continue;
        const int xr0 = 2 * xl0 + px;            // real output x
        const int xr1 = 2 * xl1 + px;
        #pragma unroll
        for (int j = 0; j < 4; ++j) {
            const int co = 16 * j + 2 * tg;
            const float b0 = bias[co];
            const float b1 = bias[co + 1];
            const float b8 = bias[co + 8];
            const float b9 = bias[co + 9];
            float* e = acc[i][j].x;
            if (v0) {
                float* q0 = obase + (long long)xr0 * C + co;
                q0[0] = tanhf(e[0] - b0);
                q0[1] = tanhf(e[1] - b1);
                q0[8] = tanhf(e[4] - b8);
                q0[9] = tanhf(e[5] - b9);
            }
            if (v1) {
                float* q1 = obase + (long long)xr1 * C + co;
                q1[0] = tanhf(e[2] - b0);
                q1[1] = tanhf(e[3] - b1);
                q1[8] = tanhf(e[6] - b8);
                q1[9] = tanhf(e[7] - b9);
            }
        }
    }
}

// ---------------------------------------------------------------------------
// host wrappers
// ---------------------------------------------------------------------------
torch::Tensor nchw_to_nhwc_pad_cuda(torch::Tensor x, int64_t cp) {
    TORCH_CHECK(x.is_cuda() && x.scalar_type() == at::kFloat, "need float32 CUDA tensor");
    TORCH_CHECK(x.dim() == 4, "x must be NCHW");
    auto xc = x.contiguous();
    const int n = xc.size(0), C = xc.size(1), H = xc.size(2), W = xc.size(3);
    TORCH_CHECK(C == 64 && H == 256 && W == 256, "specialized kernel: C=64,H=W=256");
    const int RP = H + 2;
    auto xp = torch::empty({(long long)n, (long long)RP, cp, (long long)C},
                           xc.options());
    dim3 grid(n, RP);
    cudaStream_t stream = at::cuda::getCurrentCUDAStream();
    nchw_to_nhwc_pad_kernel<64, 256, 256, 258, 290><<<grid, 256, 0, stream>>>(
        xc.data_ptr<float>(), xp.data_ptr<float>(), n);
    return xp;
}

torch::Tensor tconv_gemm_cuda(torch::Tensor xp, torch::Tensor wq,
                              torch::Tensor bias, int64_t n_batch) {
    TORCH_CHECK(xp.is_cuda() && wq.is_cuda() && bias.is_cuda(), "CUDA tensors required");
    const int n = (int)n_batch;
    const int HOUT = 513;
    auto out = torch::empty({(long long)n, (long long)HOUT, (long long)HOUT, 64LL},
                            xp.options());
    dim3 grid(9, 33, n * 4);
    cudaStream_t stream = at::cuda::getCurrentCUDAStream();
    tconv_gemm_kernel<64, 256, 258, 290, 513><<<grid, 256, 0, stream>>>(
        xp.data_ptr<float>(), wq.data_ptr<float>(), bias.data_ptr<float>(),
        out.data_ptr<float>());
    return out;
}
"""

custom_cpp_source = """
torch::Tensor nchw_to_nhwc_pad_cuda(torch::Tensor x, int64_t cp);
torch::Tensor tconv_gemm_cuda(torch::Tensor xp, torch::Tensor wq, torch::Tensor bias, int64_t n_batch);
"""

custom_ops = load_inline(
    name="fused_tconv_bias_tanh_v3",
    cpp_sources=custom_cpp_source,
    cuda_sources=custom_source,
    functions=["nchw_to_nhwc_pad_cuda", "tconv_gemm_cuda"],
    verbose=False,
    extra_cflags=["-O3"],
    extra_cuda_cflags=["-O3", "-use_fast_math", "-arch=sm_80"],
)


class ModelNew(nn.Module):
    """
    Fully fused custom implementation:
      NCHW->padded NHWC conversion kernel, then a single TF32 tensor-core
      implicit-GEMM kernel that computes the transposed convolution with
      bias-subtraction and tanh fused in its epilogue, emitting the result
      directly in channels_last layout.
    Specialized for C_in=C_out=64, H=W=256, k=4, s=2, p=1, op=1; falls back
    to the PyTorch reference otherwise.
    """
    def __init__(self, in_channels, out_channels, kernel_size, bias_shape, stride=2, padding=1, output_padding=1):
        super(ModelNew, self).__init__()
        self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,
                                                 stride=stride, padding=padding,
                                                 output_padding=output_padding)
        self.bias = nn.Parameter(torch.randn(bias_shape))
        self._specialized = (in_channels == 64 and out_channels == 64
                             and kernel_size == 4 and stride == 2
                             and padding == 1 and output_padding == 1)
        self._wq = None

    def _build_swizzle(self):
        w = self.conv_transpose.weight.detach()  # [Ci, Co, 4, 4]
        Ci, Co = w.shape[0], w.shape[1]
        ky = ((3, 1), (2, 0))   # ky[py][dr]
        kx = ((3, 1), (2, 0))   # kx[px][dc]
        wq = torch.empty(4, 4 * Ci, Co, device=w.device, dtype=torch.float32)
        for p in range(4):
            py, px = p >> 1, p & 1
            for t in range(4):
                dr, dc = t >> 1, t & 1
                wq[p, t * Ci:(t + 1) * Ci, :] = w[:, :, ky[py][dr], kx[px][dc]].float()
        self._wq = wq.contiguous()

    def forward(self, x):
        if not self._specialized:
            return torch.tanh(self.conv_transpose(x) - self.bias)
        if self._wq is None or self._wq.device != x.device:
            self._build_swizzle()
        n = x.shape[0]
        xp = custom_ops.nchw_to_nhwc_pad_cuda(x, 290)
        out = custom_ops.tconv_gemm_cuda(xp, self._wq, self.bias, n)
        # return as a channels_last NCHW-view tensor (values identical)
        return out.permute(0, 3, 1, 2)
```
Result of evaluating it:
The solution failed to compile. Error output:
```
RuntimeError: Error building extension 'fused_tconv_bias_tanh_v3': [1/3] c++ -MMD -MF main.o.d -DTORCH_EXTENSION_NAME=fused_tconv_bias_tanh_v3 -DTORCH_API_INCLUDE_EXTENSION_H -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include/torch/csrc/api/include -isystem /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/include -isystem /usr/include/python3.12 -fPIC -std=c++20 -O3 -c /srv/jobs/1791520830560779785-4064865-0/build/fused_tconv_bias_tanh_v3/main.cpp -o main.o 
[2/3] /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/bin/nvcc -MD -MF cuda.cuda.o.d -DTORCH_EXTENSION_NAME=fused_tconv_bias_tanh_v3 -DTORCH_API_INCLUDE_EXTENSION_H -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include/torch/csrc/api/include -isystem /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/include -isystem /usr/include/python3.12 -D__CUDA_NO_HALF_OPERATORS__ -D__CUDA_NO_HALF_CONVERSIONS__ -D__CUDA_NO_BFLOAT16_CONVERSIONS__ -D__CUDA_NO_HALF2_OPERATORS__ --expt-relaxed-constexpr --compiler-options '-fPIC' -O3 -use_fast_math -arch=sm_80 -std=c++20 -c /srv/jobs/1791520830560779785-4064865-0/build/fused_tconv_bias_tanh_v3/cuda.cu -o cuda.cuda.o 
FAILED: [code=255] cuda.cuda.o 
/opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/bin/nvcc -MD -MF cuda.cuda.o.d -DTORCH_EXTENSION_NAME=fused_tconv_bias_tanh_v3 -DTORCH_API_INCLUDE_EXTENSION_H -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include/torch/csrc/api/include -isystem /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/include -isystem /usr/include/python3.12 -D__CUDA_NO_HALF_OPERATORS__ -D__CUDA_NO_HALF_CONVERSIONS__ -D__CUDA_NO_BFLOAT16_CONVERSIONS__ -D__CUDA_NO_HALF2_OPERATORS__ --expt-relaxed-constexpr --compiler-options '-fPIC' -O3 -use_fast_math -arch=sm_80 -std=c++20 -c /srv/jobs/1791520830560779785-4064865-0/build/fused_tconv_bias_tanh_v3/cuda.cu -o cuda.cuda.o 
ptxas error   : Entry function '_Z23nchw_to_nhwc_pad_kernelILi64ELi256ELi256ELi258ELi290EEvPKfPfi' uses too much shared data (0x10800 bytes, 0xc000 max)
ninja: build stopped: subcommand failed.

```

The fastest correct solution so far (1.420x speedup) is:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
from torch.utils.cpp_extension import load_inline

torch.backends.cudnn.benchmark = True
torch.backends.cudnn.allow_tf32 = True

# Fused bias-subtraction + tanh that works directly on the cuDNN NHWC
# (channels_last) output of the transposed convolution, eliminating the
# expensive NHWC->NCHW layout conversion kernels. In NHWC, consecutive
# elements are consecutive channels, so a float4 covers channels
# c..c+3 and the bias can be loaded as one float4.
fused_sub_bias_tanh_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>
#include <cstdint>

// ---------------- channels_last (NHWC) kernels ----------------
// Requires C % 4 == 0 and 16B-aligned pointers.
__global__ void sub_bias_tanh_nhwc_vec4_kernel(const float4* __restrict__ x,
                                               const float4* __restrict__ bias4,
                                               float4* __restrict__ out,
                                               const unsigned int C4,
                                               const unsigned int total4) {
    unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
    if (i < total4) {
        float4 b = bias4[i % C4];
        float4 v = x[i];
        v.x = tanhf(v.x - b.x);
        v.y = tanhf(v.y - b.y);
        v.z = tanhf(v.z - b.z);
        v.w = tanhf(v.w - b.w);
        out[i] = v;
    }
}

__global__ void sub_bias_tanh_nhwc_kernel(const float* __restrict__ x,
                                          const float* __restrict__ bias,
                                          float* __restrict__ out,
                                          const long long C,
                                          const long long total) {
    long long i = (long long)blockIdx.x * blockDim.x + threadIdx.x;
    if (i < total) {
        out[i] = tanhf(x[i] - bias[i % C]);
    }
}

// ---------------- NCHW fallback kernels ----------------
__global__ void sub_bias_tanh_nchw_vec4_kernel(const float4* __restrict__ x,
                                               const float* __restrict__ bias,
                                               float4* __restrict__ out,
                                               const unsigned int C,
                                               const unsigned int HW4,
                                               const unsigned int total4) {
    unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
    if (i < total4) {
        float b = bias[(i / HW4) % C];
        float4 v = x[i];
        v.x = tanhf(v.x - b);
        v.y = tanhf(v.y - b);
        v.z = tanhf(v.z - b);
        v.w = tanhf(v.w - b);
        out[i] = v;
    }
}

__global__ void sub_bias_tanh_nchw_kernel(const float* __restrict__ x,
                                          const float* __restrict__ bias,
                                          float* __restrict__ out,
                                          const long long C,
                                          const long long HW,
                                          const long long total) {
    long long i = (long long)blockIdx.x * blockDim.x + threadIdx.x;
    if (i < total) {
        out[i] = tanhf(x[i] - bias[(i / HW) % C]);
    }
}

static inline bool aligned16(const void* p) {
    return (reinterpret_cast<uintptr_t>(p) & 15) == 0;
}

torch::Tensor sub_bias_tanh_cuda(torch::Tensor x, torch::Tensor bias) {
    TORCH_CHECK(x.is_cuda() && bias.is_cuda(), "inputs must be CUDA tensors");
    TORCH_CHECK(x.scalar_type() == at::kFloat && bias.scalar_type() == at::kFloat,
                "inputs must be float32");
    TORCH_CHECK(x.dim() == 4, "x must be 4D (N, C, H, W)");

    auto bias_c = bias.contiguous();
    const long long C = x.size(1);
    const long long total = x.numel();
    TORCH_CHECK(bias_c.numel() == C, "bias must have exactly C elements");

    cudaStream_t stream = at::cuda::getCurrentCUDAStream();
    constexpr int block = 256;
    const float* b_ptr = bias_c.data_ptr<float>();
    const bool b_al = aligned16(b_ptr);

    if (x.is_contiguous(at::MemoryFormat::ChannelsLast)) {
        auto out = torch::empty_like(x);  // preserves channels_last
        const float* x_ptr = x.data_ptr<float>();
        float* o_ptr = out.data_ptr<float>();
        if (total > 0 && (C % 4 == 0) && b_al && aligned16(x_ptr) && aligned16(o_ptr)
            && (total / 4) < 0xFFFFFFFFLL) {
            const unsigned int total4 = (unsigned int)(total / 4);
            const unsigned int C4 = (unsigned int)(C / 4);
            const unsigned int blocks = (total4 + block - 1) / block;
            sub_bias_tanh_nhwc_vec4_kernel<<<blocks, block, 0, stream>>>(
                reinterpret_cast<const float4*>(x_ptr),
                reinterpret_cast<const float4*>(b_ptr),
                reinterpret_cast<float4*>(o_ptr), C4, total4);
        } else if (total > 0) {
            const long long blocks = (total + block - 1) / block;
            sub_bias_tanh_nhwc_kernel<<<blocks, block, 0, stream>>>(x_ptr, b_ptr, o_ptr, C, total);
        }
        return out;
    }

    if (x.is_contiguous()) {  // NCHW fallback
        auto out = torch::empty_like(x);
        const float* x_ptr = x.data_ptr<float>();
        float* o_ptr = out.data_ptr<float>();
        const long long HW = (long long)x.size(2) * x.size(3);
        if (total > 0 && (HW % 4 == 0) && b_al && aligned16(x_ptr) && aligned16(o_ptr)
            && (total / 4) < 0xFFFFFFFFLL) {
            const unsigned int total4 = (unsigned int)(total / 4);
            const unsigned int blocks = (total4 + block - 1) / block;
            sub_bias_tanh_nchw_vec4_kernel<<<blocks, block, 0, stream>>>(
                reinterpret_cast<const float4*>(x_ptr), b_ptr,
                reinterpret_cast<float4*>(o_ptr),
                (unsigned int)C, (unsigned int)(HW / 4), total4);
        } else if (total > 0) {
            const long long blocks = (total + block - 1) / block;
            sub_bias_tanh_nchw_kernel<<<blocks, block, 0, stream>>>(x_ptr, b_ptr, o_ptr, C, HW, total);
        }
        return out;
    }

    // Non-contiguous generic fallback: make it channels_last once, then fast path.
    auto x_c = x.contiguous(at::MemoryFormat::ChannelsLast);
    auto out = torch::empty_like(x_c);
    const float* x_ptr = x_c.data_ptr<float>();
    float* o_ptr = out.data_ptr<float>();
    if (total > 0 && (C % 4 == 0) && b_al && aligned16(x_ptr) && aligned16(o_ptr)
        && (total / 4) < 0xFFFFFFFFLL) {
        const unsigned int total4 = (unsigned int)(total / 4);
        const unsigned int C4 = (unsigned int)(C / 4);
        const unsigned int blocks = (total4 + block - 1) / block;
        sub_bias_tanh_nhwc_vec4_kernel<<<blocks, block, 0, stream>>>(
            reinterpret_cast<const float4*>(x_ptr),
            reinterpret_cast<const float4*>(b_ptr),
            reinterpret_cast<float4*>(o_ptr), C4, total4);
    } else if (total > 0) {
        const long long blocks = (total + block - 1) / block;
        sub_bias_tanh_nhwc_kernel<<<blocks, block, 0, stream>>>(x_ptr, b_ptr, o_ptr, C, total);
    }
    return out;
}
"""

fused_sub_bias_tanh_cpp_source = (
    "torch::Tensor sub_bias_tanh_cuda(torch::Tensor x, torch::Tensor bias);"
)

fused_sub_bias_tanh = load_inline(
    name="fused_sub_bias_tanh_nhwc_v2",
    cpp_sources=fused_sub_bias_tanh_cpp_source,
    cuda_sources=fused_sub_bias_tanh_source,
    functions=["sub_bias_tanh_cuda"],
    verbose=False,
    extra_cflags=["-O3"],
    extra_cuda_cflags=["-O3", "-use_fast_math"],
)


class ModelNew(nn.Module):
    """
    Optimized model: keep the ConvTranspose2d on cuDNN but run the whole
    pipeline in channels_last so the TF32 dgrad kernel consumes/produces
    NHWC directly (no layout-conversion kernels), then apply a single
    fused, float4-vectorized bias-subtract + tanh kernel on the NHWC data.
    """
    def __init__(self, in_channels, out_channels, kernel_size, bias_shape, stride=2, padding=1, output_padding=1):
        super(ModelNew, self).__init__()
        self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size,
                                                 stride=stride, padding=padding,
                                                 output_padding=output_padding)
        self.bias = nn.Parameter(torch.randn(bias_shape))
        with torch.no_grad():
            self.conv_transpose.weight.data = self.conv_transpose.weight.data.to(
                memory_format=torch.channels_last)

    def forward(self, x):
        x = x.to(memory_format=torch.channels_last)
        x = self.conv_transpose(x)
        return fused_sub_bias_tanh.sub_bias_tanh_cuda(x, self.bias)
```

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.
