You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Model that performs matrix multiplication, max pooling, sum, and scaling.
    """
    def __init__(self, in_features, out_features, kernel_size, scale_factor):
        super(Model, self).__init__()
        self.matmul = nn.Linear(in_features, out_features)
        self.max_pool = nn.MaxPool1d(kernel_size)
        self.scale_factor = scale_factor

    def forward(self, x):
        """
        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, in_features).

        Returns:
            torch.Tensor: Output tensor of shape (batch_size, out_features).
        """
        x = self.matmul(x)
        x = self.max_pool(x.unsqueeze(1)).squeeze(1)
        x = torch.sum(x, dim=1)
        x = x * self.scale_factor
        return x

batch_size = 128
in_features = 32768
out_features = 32768
kernel_size = 2
scale_factor = 0.5

def get_inputs():
    return [torch.rand(batch_size, in_features)]

def get_init_inputs():
    return [in_features, out_features, kernel_size, scale_factor]
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 3 of 6 for this task. Your previous solution (turn 2) was:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# TF32 tensor-core math is allowed for the FP32 matmul (matches PyTorch reference behavior).
try:
    torch.backends.cuda.matmul.allow_tf32 = True
    torch.backends.cudnn.allow_tf32 = True
except Exception:
    pass

# Custom fused kernel:
#   out[b] = scale * sum_j max( (x @ W^T + bias)[b, 2j], (x @ W^T + bias)[b, 2j+1] )
# implemented as a TF32 tensor-core GEMM (M=batch<=128, N=out_features, K=in_features)
# with the max-pool + sum + scale epilogue fused directly into the GEMM, so the
# [batch, out_features] matrix is never materialized in DRAM.
fused_gemm_cuda_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>
#include <cstdint>

// tile configuration
constexpr int M_T = 128;      // block tile rows (covers whole batch <= 128)
constexpr int N_T = 128;      // block tile cols
constexpr int K_T = 32;       // k slice per pipeline stage
constexpr int STAGES = 2;     // cp.async pipeline depth
constexpr int PAD = 4;        // shared-memory row padding (bank-conflict free)
constexpr int A_STRIDE = K_T + PAD;
constexpr int B_STRIDE = K_T + PAD;
constexpr int NTHREADS = 256;
constexpr int NBUF = M_T * A_STRIDE + N_T * B_STRIDE;  // floats per stage

__device__ __forceinline__ uint32_t smem_u32(const void* p) {
    return static_cast<uint32_t>(__cvta_generic_to_shared(p));
}

__device__ __forceinline__ void cp_async16(void* smem, const void* gmem) {
    asm volatile("cp.async.ca.shared.global [%0], [%1], 16;\n" ::
                 "r"(smem_u32(smem)), "l"(gmem));
}

__device__ __forceinline__ void cp_commit() {
    asm volatile("cp.async.commit_group;\n" ::);
}

__device__ __forceinline__ void cp_wait1() {
    asm volatile("cp.async.wait_group 1;\n" ::);
}

__device__ __forceinline__ void cp_wait0() {
    asm volatile("cp.async.wait_group 0;\n" ::);
}

__device__ __forceinline__ uint32_t f2tf32(float x) {
    uint32_t r;
    asm volatile("cvt.rna.tf32.f32 %0, %1;\n" : "=r"(r) : "f"(x));
    return r;
}

__device__ __forceinline__ void mma_tf32(float &c0, float &c1, float &c2, float &c3,
                                         uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3,
                                         uint32_t b0, uint32_t b1) {
    asm volatile(
        "mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 "
        "{%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%0,%1,%2,%3};\n"
        : "+f"(c0), "+f"(c1), "+f"(c2), "+f"(c3)
        : "r"(a0), "r"(a1), "r"(a2), "r"(a3), "r"(b0), "r"(b1));
}

__global__ void __launch_bounds__(NTHREADS, 2)
fused_gemm_maxsum_kernel(const float* __restrict__ X,
                         const float* __restrict__ W,
                         const float* __restrict__ bias,
                         float* __restrict__ out,
                         int M, int N, int K, float scale) {
    extern __shared__ float smem[];
    float* As = smem;
    float* Bs = smem + STAGES * M_T * A_STRIDE;

    const int tid = threadIdx.x;
    const int mrow = tid >> 1;            // 0..127
    const int mcol = (tid & 1) * 16;      // 0 or 16
    const int brow = tid >> 1;            // 0..127
    const int bcol = (tid & 1) * 16;

    const int lane = tid & 31;
    const int warp = tid >> 5;            // 0..7 -> m strip
    const int wm = warp * 16;             // warp base row in tile
    const int gid = lane >> 2;            // 0..7
    const int tig = lane & 3;             // 0..3
    // A fragment element coordinates (m16n8k8)
    const int ar0 = wm + gid;
    const int ar1 = wm + gid + 8;
    const int ac0 = tig;
    const int ac1 = tig + 4;
    // B fragment element coordinates
    const int br0 = tig;
    const int br1 = tig + 4;
    const int bc = gid;

    float acc[8][4];
    #pragma unroll
    for (int i = 0; i < 8; ++i) {
        #pragma unroll
        for (int j = 0; j < 4; ++j) acc[i][j] = 0.0f;
    }

    const int kt_count = K >> 5;  // K / 32 (K guaranteed multiple of 32)

    // global pointers for the loaders
    const float* xg = X + (int64_t)mrow * K + mcol;
    const float* wg = W + (int64_t)(blockIdx.x * N_T + brow) * K + bcol;

    // stage loader: loads k-tile kt into buffer buf
    auto load_stage = [&](int kt, int buf) {
        float* as = As + buf * M_T * A_STRIDE;
        float* bs = Bs + buf * N_T * B_STRIDE;
        const int koff = kt * K_T;
        #pragma unroll
        for (int i = 0; i < 2; ++i) {
            cp_async16(as + (mrow + i * M_T) * 0 + mrow * A_STRIDE + mcol + i * 8,
                       xg + koff + i * 8);
        }
        #pragma unroll
        for (int i = 0; i < 2; ++i) {
            cp_async16(bs + brow * B_STRIDE + bcol + i * 8,
                       wg + koff + i * 8);
        }
    };

    load_stage(0, 0);
    cp_commit();
    load_stage(1, 1);
    cp_commit();

    int buf = 0;
    for (int kt = 0; kt < kt_count; ++kt) {
        if (kt + 2 < kt_count) {
            cp_wait1();
        } else {
            cp_wait0();
        }
        __syncthreads();

        const float* as = As + buf * M_T * A_STRIDE;
        const float* bs = Bs + buf * N_T * B_STRIDE;

        #pragma unroll
        for (int kk = 0; kk < 4; ++kk) {   // 4 x k8 steps per 32-wide tile
            const int kb = kk * 8;
            uint32_t a[4];
            a[0] = f2tf32(as[ar0 * A_STRIDE + kb + ac0]);
            a[1] = f2tf32(as[ar1 * A_STRIDE + kb + ac0]);
            a[2] = f2tf32(as[ar0 * A_STRIDE + kb + ac1]);
            a[3] = f2tf32(as[ar1 * A_STRIDE + kb + ac1]);
            #pragma unroll
            for (int nn = 0; nn < 8; ++nn) {
                uint32_t b0 = f2tf32(bs[(nn * 8 + bc) * B_STRIDE + kb + br0]);
                uint32_t b1 = f2tf32(bs[(nn * 8 + bc) * B_STRIDE + kb + br1]);
                mma_tf32(acc[nn][0], acc[nn][1], acc[nn][2], acc[nn][3],
                         a[0], a[1], a[2], a[3], b0, b1);
            }
        }
        __syncthreads();
        buf ^= 1;
        if (kt + 2 < kt_count) {
            load_stage(kt + 2, buf);
        }
        cp_commit();
    }

    // fused epilogue: bias + pairwise max + scale + atomic accumulate
    const float* biasp = bias + blockIdx.x * N_T;
    float part = 0.0f;
    #pragma unroll
    for (int p = 0; p < 4; ++p) {
        const float* bp = biasp + p * 16 + tig * 2;
        const float b0 = bp[0];
        const float b1 = bp[1];
        const float b2 = bp[8];
        const float b3 = bp[9];
        float m0 = fmaxf(acc[2 * p][0]     + b0, acc[2 * p + 1][0] + b1);
        float m1 = fmaxf(acc[2 * p][1]     + b2, acc[2 * p + 1][1] + b3);
        float m2 = fmaxf(acc[2 * p][2]     + b0, acc[2 * p + 1][2] + b1);
        float m3 = fmaxf(acc[2 * p][3]     + b2, acc[2 * p + 1][3] + b3);
        part += (m0 + m1) + (m2 + m3);
    }
    // reduce tig (4 threads) -> lanes 0,4,8,...,28 hold row sums
    part += __shfl_down_sync(0xffffffffu, part, 2);
    part += __shfl_down_sync(0xffffffffu, part, 1);
    if (tig == 0) {
        atomicAdd(&out[wm + gid],     part * scale);
        atomicAdd(&out[wm + gid + 8], part * scale);
    }
}

torch::Tensor fused_gemm_maxsum_cuda(torch::Tensor x, torch::Tensor w,
                                     torch::Tensor b, double scale) {
    TORCH_CHECK(x.is_cuda() && w.is_cuda() && b.is_cuda(), "CUDA tensors required");
    TORCH_CHECK(x.scalar_type() == torch::kFloat32, "x must be float32");
    TORCH_CHECK(w.scalar_type() == torch::kFloat32, "w must be float32");
    TORCH_CHECK(b.scalar_type() == torch::kFloat32, "b must be float32");
    auto xc = x.contiguous();
    auto wc = w.contiguous();
    auto bc = b.contiguous();
    const int M = (int)xc.size(0);
    const int K = (int)xc.size(1);
    const int N = (int)wc.size(0);
    TORCH_CHECK(wc.size(1) == K, "shape mismatch");
    TORCH_CHECK(M <= M_T, "batch too large for fused kernel");
    TORCH_CHECK((N % N_T) == 0, "out_features must be a multiple of 128");
    TORCH_CHECK((K % K_T) == 0, "in_features must be a multiple of 32");

    auto out = torch::zeros({M}, xc.options());
    const int smem_bytes = STAGES * NBUF * sizeof(float);

    static int configured_smem = 0;
    if (!configured_smem) {
        cudaFuncSetAttribute(fused_gemm_maxsum_kernel,
                             cudaFuncAttributeMaxDynamicSharedMemorySize,
                             smem_bytes);
        configured_smem = 1;
    }

    dim3 grid(N / N_T);
    auto stream = at::cuda::getCurrentCUDAStream();
    fused_gemm_maxsum_kernel<<<grid, NTHREADS, smem_bytes, stream>>>(
        xc.data_ptr<float>(), wc.data_ptr<float>(), bc.data_ptr<float>(),
        out.data_ptr<float>(), M, N, K, (float)scale);
    return out;
}
"""

fused_gemm_cpp_source = (
    "torch::Tensor fused_gemm_maxsum_cuda(torch::Tensor x, torch::Tensor w, "
    "torch::Tensor b, double scale);"
)

fused_gemm = load_inline(
    name="fused_gemm_maxpool_sum",
    cpp_sources=fused_gemm_cpp_source,
    cuda_sources=fused_gemm_cuda_source,
    functions=["fused_gemm_maxsum_cuda"],
    verbose=False,
    extra_cuda_cflags=["-O3"],
)


class ModelNew(nn.Module):
    """
    Optimized model: single fused TF32 tensor-core CUDA kernel computing
    Linear -> MaxPool1d(2) -> sum -> scale in one pass (weights are streamed
    exactly once from DRAM; the full [batch, out_features] product is never
    written to memory). Falls back to the PyTorch reference path for
    unsupported shapes/devices.
    """

    def __init__(self, in_features, out_features, kernel_size, scale_factor):
        super(ModelNew, self).__init__()
        self.matmul = nn.Linear(in_features, out_features)
        self.max_pool = nn.MaxPool1d(kernel_size)
        self.kernel_size = kernel_size
        self.scale_factor = scale_factor
        self.in_features = in_features
        self.out_features = out_features
        self.fused_op = fused_gemm

    def forward(self, x):
        if (x.is_cuda and x.dtype == torch.float32
                and self.kernel_size == 2
                and x.size(0) <= 128
                and (self.out_features % 128) == 0
                and (self.in_features % 32) == 0):
            return self.fused_op.fused_gemm_maxsum_cuda(
                x, self.matmul.weight, self.matmul.bias,
                float(self.scale_factor))
        # Generic fallback (reference path).
        x = F.linear(x, self.matmul.weight, self.matmul.bias)
        x = self.max_pool(x.unsqueeze(1)).squeeze(1)
        x = torch.sum(x, dim=1)
        x = x * self.scale_factor
        return x
```
Result of evaluating it:
The solution compiled and ran but its output did not match the reference. Details:
```
{"avg_difference": ["453485440.000000", "487306144.000000", "470353216.000000", "447107808.000000", "457209376.000000"], "correctness_issue": "Output mismatch", "correctness_trials": "(0 / 5)", "max_difference": ["4403145216.000000", "4898609664.000000", "4683260416.000000", "4368373760.000000", "4993266176.000000"]}
```

The fastest correct solution so far (1.015x speedup) is:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# TF32 tensor-core math is allowed for the FP32 matmul (matches PyTorch reference behavior).
try:
    torch.backends.cuda.matmul.allow_tf32 = True
    torch.backends.cudnn.allow_tf32 = True
except Exception:
    pass

# Fused kernel: max-pool (kernel_size=2) + sum over features + scaling.
# For each batch row: out[b] = scale * sum_i max(x[b, 2i], x[b, 2i+1])
fused_maxpool_sum_scale_cuda_source = r"""
#include <torch/extension.h>
#include <cuda_runtime.h>
#include <cstdint>

constexpr int BLOCK_SIZE = 256;

__global__ void maxpool_sum_scale_kernel(const float* __restrict__ x,
                                         float* __restrict__ out,
                                         int64_t out_features,
                                         float scale) {
    const int64_t row = blockIdx.x;
    const float* p = x + row * out_features;
    const int64_t num_pairs = out_features >> 1;

    float sum = 0.0f;

    if ((reinterpret_cast<uintptr_t>(p) & 0xF) == 0) {
        // 16-byte aligned: use vectorized float4 loads (2 pairs per load).
        const float4* p4 = reinterpret_cast<const float4*>(p);
        const int64_t num_vec = num_pairs >> 1;
        for (int64_t i = threadIdx.x; i < num_vec; i += BLOCK_SIZE) {
            float4 v = p4[i];
            sum += fmaxf(v.x, v.y) + fmaxf(v.z, v.w);
        }
        // Tail pair when the number of pairs is odd.
        if ((num_pairs & 1) && threadIdx.x == 0) {
            const int64_t i = num_pairs - 1;
            sum += fmaxf(p[2 * i], p[2 * i + 1]);
        }
    } else {
        for (int64_t i = threadIdx.x; i < num_pairs; i += BLOCK_SIZE) {
            sum += fmaxf(p[2 * i], p[2 * i + 1]);
        }
    }

    // Warp-level reduction.
    #pragma unroll
    for (int offset = 16; offset > 0; offset >>= 1) {
        sum += __shfl_down_sync(0xffffffffu, sum, offset);
    }

    __shared__ float shared[BLOCK_SIZE / 32];
    const int lane = threadIdx.x & 31;
    const int wid  = threadIdx.x >> 5;
    if (lane == 0) {
        shared[wid] = sum;
    }
    __syncthreads();

    if (wid == 0) {
        sum = (lane < BLOCK_SIZE / 32) ? shared[lane] : 0.0f;
        #pragma unroll
        for (int offset = 16; offset > 0; offset >>= 1) {
            sum += __shfl_down_sync(0xffffffffu, sum, offset);
        }
        if (lane == 0) {
            out[row] = sum * scale;
        }
    }
}

torch::Tensor maxpool_sum_scale_cuda(torch::Tensor x, double scale) {
    TORCH_CHECK(x.is_cuda(), "x must be a CUDA tensor");
    TORCH_CHECK(x.scalar_type() == torch::kFloat32, "x must be float32");
    auto xc = x.contiguous();
    const int64_t batch = xc.size(0);
    const int64_t out_features = xc.size(1);

    auto out = torch::empty({batch}, xc.options());

    dim3 grid(static_cast<unsigned int>(batch));
    maxpool_sum_scale_kernel<<<grid, BLOCK_SIZE>>>(
        xc.data_ptr<float>(),
        out.data_ptr<float>(),
        out_features,
        static_cast<float>(scale));

    return out;
}
"""

fused_maxpool_sum_scale_cpp_source = (
    "torch::Tensor maxpool_sum_scale_cuda(torch::Tensor x, double scale);"
)

fused_maxpool_sum_scale = load_inline(
    name="fused_maxpool_sum_scale",
    cpp_sources=fused_maxpool_sum_scale_cpp_source,
    cuda_sources=fused_maxpool_sum_scale_cuda_source,
    functions=["maxpool_sum_scale_cuda"],
    verbose=False,
    extra_cuda_cflags=["-O3"],
)


class ModelNew(nn.Module):
    """
    Optimized model: cuBLAS (TF32) linear layer + a single fused CUDA kernel
    performing max-pool (kernel_size=2), feature sum and scaling in one pass.
    """

    def __init__(self, in_features, out_features, kernel_size, scale_factor):
        super(ModelNew, self).__init__()
        self.matmul = nn.Linear(in_features, out_features)
        self.max_pool = nn.MaxPool1d(kernel_size)
        self.kernel_size = kernel_size
        self.scale_factor = scale_factor
        self.fused_op = fused_maxpool_sum_scale

    def forward(self, x):
        x = F.linear(x, self.matmul.weight, self.matmul.bias)
        if self.kernel_size == 2 and x.is_cuda and x.dtype == torch.float32:
            return self.fused_op.maxpool_sum_scale_cuda(
                x, float(self.scale_factor))
        # Generic fallback (reference path).
        x = self.max_pool(x.unsqueeze(1)).squeeze(1)
        x = torch.sum(x, dim=1)
        x = x * self.scale_factor
        return x
```

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.


Precision rule: the timed forward must compute in FP32 (TF32 tensor-core math is allowed, as in the PyTorch reference). Do not cast inputs, weights or intermediate results to float16 or bfloat16 and do not call half-precision kernels in forward().
