You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Model that performs matrix multiplication, max pooling, sum, and scaling.
    """
    def __init__(self, in_features, out_features, kernel_size, scale_factor):
        super(Model, self).__init__()
        self.matmul = nn.Linear(in_features, out_features)
        self.max_pool = nn.MaxPool1d(kernel_size)
        self.scale_factor = scale_factor

    def forward(self, x):
        """
        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, in_features).

        Returns:
            torch.Tensor: Output tensor of shape (batch_size, out_features).
        """
        x = self.matmul(x)
        x = self.max_pool(x.unsqueeze(1)).squeeze(1)
        x = torch.sum(x, dim=1)
        x = x * self.scale_factor
        return x

batch_size = 128
in_features = 32768
out_features = 32768
kernel_size = 2
scale_factor = 0.5

def get_inputs():
    return [torch.rand(batch_size, in_features)]

def get_init_inputs():
    return [in_features, out_features, kernel_size, scale_factor]
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 5 of 6 for this task. Your previous solution (turn 4) was:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Allow tensor-core math for any fp32 fallback matmuls.
torch.backends.cuda.matmul.allow_tf32 = True
torch.backends.cudnn.allow_tf32 = True
# Keep fp16 GEMM reductions in fp32 for accuracy.
torch.backends.cuda.matmul.allow_fp16_reduced_precision_reduction = False

# The workload is dominated by a (128 x 32768) @ (32768 x 32768) GEMM whose fp16
# weight matrix is ~2.1 GB, i.e. it is HBM-bandwidth-bound. With batch=128 a
# single GEMM launch creates only ~256 thread blocks (128x128 tiles), barely two
# waves on a 108-SM A100, so the tail leaves the memory system idle. We instead
# split the K dimension into 4 chunks issued as ONE strided-batched GEMM
# (torch.bmm -> cuBLAS), giving 4x the thread blocks and much better SM/HBM
# utilization. cuBLAS accumulates each chunk in fp32 on tensor cores. A fused
# custom kernel then reduces the chunk partials, adds the bias, applies
# max-pool(k=2), sums over features and scales -- reading the fp16 partials once
# and writing only `batch` floats, with fp32 accumulation.
_fused_cuda_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAException.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>

#define THREADS 512

__device__ __forceinline__ float blockReduceSumF(float val) {
    __shared__ float shared[32];
    const int lane = threadIdx.x & 31;
    const int wid  = threadIdx.x >> 5;
    #pragma unroll
    for (int offset = 16; offset > 0; offset >>= 1)
        val += __shfl_down_sync(0xffffffffu, val, offset);
    if (lane == 0) shared[wid] = val;
    __syncthreads();
    const int nwarp = (blockDim.x + 31) >> 5;
    if (wid == 0) {
        val = (lane < nwarp) ? shared[lane] : 0.0f;
        #pragma unroll
        for (int offset = 16; offset > 0; offset >>= 1)
            val += __shfl_down_sync(0xffffffffu, val, offset);
    }
    return val;  // only thread 0 holds the block total
}

// P: (CHUNKS, rows, N) fp16 partial sums of the K-split GEMM.
// bias: (N) fp32.
// out[r] = scale * sum_j max(bias[2j]   + sum_c P[c,r,2j],
//                            bias[2j+1] + sum_c P[c,r,2j+1])
// One float4 load of P covers 8 halfs = 4 pool pairs. Requires N % 8 == 0.
template<int CHUNKS>
__global__ void chunked_partial_maxpool2_sum_scale_kernel(
    const __half* __restrict__ P, const float* __restrict__ bias,
    float* __restrict__ out, const int rows, const long long N,
    const float scale)
{
    const int r = blockIdx.x;
    const long long row_off = (long long)r * N;
    const long long cstride = (long long)rows * N;
    const long long nv = N >> 3;  // groups of 8 halfs
    const float4* __restrict__ b4 = reinterpret_cast<const float4*>(bias);

    float acc = 0.0f;
    for (long long i = threadIdx.x; i < nv; i += blockDim.x) {
        const float4 b0 = b4[2 * i];
        const float4 b1 = b4[2 * i + 1];
        float v0 = b0.x, v1 = b0.y, v2 = b0.z, v3 = b0.w;
        float v4 = b1.x, v5 = b1.y, v6 = b1.z, v7 = b1.w;
        #pragma unroll
        for (int c = 0; c < CHUNKS; ++c) {
            const float4 raw = *reinterpret_cast<const float4*>(
                P + (long long)c * cstride + row_off + (i << 3));
            const __half2* h = reinterpret_cast<const __half2*>(&raw);
            const float2 a = __half22float2(h[0]);
            const float2 b = __half22float2(h[1]);
            const float2 d = __half22float2(h[2]);
            const float2 e = __half22float2(h[3]);
            v0 += a.x; v1 += a.y; v2 += b.x; v3 += b.y;
            v4 += d.x; v5 += d.y; v6 += e.x; v7 += e.y;
        }
        acc += fmaxf(v0, v1) + fmaxf(v2, v3)
             + fmaxf(v4, v5) + fmaxf(v6, v7);
    }
    acc = blockReduceSumF(acc);
    if (threadIdx.x == 0) out[r] = acc * scale;
}

torch::Tensor chunked_partial_maxpool2_sum_scale(torch::Tensor P,
                                                 torch::Tensor bias,
                                                 double scale) {
    TORCH_CHECK(P.is_cuda() && P.dim() == 3, "P must be a 3D CUDA tensor");
    TORCH_CHECK(P.scalar_type() == torch::kFloat16, "P must be fp16");
    TORCH_CHECK(bias.is_cuda() && bias.dim() == 1, "bias must be 1D CUDA");
    TORCH_CHECK(bias.scalar_type() == torch::kFloat32, "bias must be fp32");
    auto Pc = P.contiguous();
    auto bc = bias.contiguous();
    const int chunks = Pc.size(0);
    const int rows   = Pc.size(1);
    const long long N = Pc.size(2);
    TORCH_CHECK(bc.size(0) == N, "bias size mismatch");
    TORCH_CHECK(N % 8 == 0, "N must be a multiple of 8");

    auto out = torch::empty({rows}, bc.options());
    if (rows == 0) return out;
    if (N == 0) { out.zero_(); return out; }

    const dim3 grid(rows);
    const dim3 block(THREADS);
    const float s = (float)scale;
    cudaStream_t stream = at::cuda::getCurrentCUDAStream();
    const __half* p = reinterpret_cast<const __half*>(Pc.data_ptr<at::Half>());
    const float* bi = bc.data_ptr<float>();
    float* o = out.data_ptr<float>();

    switch (chunks) {
        case 1:
            chunked_partial_maxpool2_sum_scale_kernel<1>
                <<<grid, block, 0, stream>>>(p, bi, o, rows, N, s); break;
        case 2:
            chunked_partial_maxpool2_sum_scale_kernel<2>
                <<<grid, block, 0, stream>>>(p, bi, o, rows, N, s); break;
        case 4:
            chunked_partial_maxpool2_sum_scale_kernel<4>
                <<<grid, block, 0, stream>>>(p, bi, o, rows, N, s); break;
        case 8:
            chunked_partial_maxpool2_sum_scale_kernel<8>
                <<<grid, block, 0, stream>>>(p, bi, o, rows, N, s); break;
        default:
            TORCH_CHECK(false, "unsupported chunk count");
    }
    C10_CUDA_KERNEL_LAUNCH_CHECK();
    return out;
}
"""

_fused_cpp_source = (
    "torch::Tensor chunked_partial_maxpool2_sum_scale(torch::Tensor P, torch::Tensor bias, double scale);"
)

_fused_op = load_inline(
    name="chunked_partial_maxpool_sum_scale_v1",
    cpp_sources=_fused_cpp_source,
    cuda_sources=_fused_cuda_source,
    functions=["chunked_partial_maxpool2_sum_scale"],
    verbose=False,
    extra_cuda_cflags=["-O3"],
)

_CHUNKS = 4


class ModelNew(nn.Module):
    """
    Optimized model:
      - The linear layer runs in fp16 on tensor cores. The K (in_features) dim is
        split into 4 chunks issued as a single strided-batched GEMM (torch.bmm),
        which exposes ~4x more thread blocks than one K=32768 GEMM at batch=128
        and keeps the HBM saturated (the kernel is weight-bandwidth-bound).
        The transposed fp16 weight (chunk-major layout) is built once and cached.
      - Chunk-partial reduction + bias add + max-pool(k=2) + feature sum + scale
        are fused into one custom CUDA kernel with fp32 accumulation that reads
        the fp16 partials once and writes only `batch` floats.
    """
    def __init__(self, in_features, out_features, kernel_size, scale_factor):
        super(ModelNew, self).__init__()
        self.matmul = nn.Linear(in_features, out_features)
        self.kernel_size = kernel_size
        self.scale_factor = scale_factor
        self._wT_half = None
        self._wT_ver = -1

    def forward(self, x):
        w = self.matmul.weight
        b = self.matmul.bias
        n = w.size(0)
        in_f = w.size(1)
        if (x.is_cuda and x.dtype == torch.float32 and b is not None
                and self.kernel_size == 2
                and in_f % _CHUNKS == 0 and n % 8 == 0):
            ver = w._version
            if (self._wT_half is None or self._wT_ver != ver
                    or self._wT_half.device != w.device):
                # (in_f, n) fp16, contiguous; viewing as (C, in_f/C, n) yields
                # per-chunk weight^T slices with zero runtime cost.
                self._wT_half = w.detach().half().t().contiguous()
                self._wT_ver = ver
            bs = x.size(0)
            xh = x.half()
            if not xh.is_contiguous():
                xh = xh.contiguous()
            k = in_f // _CHUNKS
            # (C, bs, k) strided view (batch stride k, row stride in_f) -- bmm
            # passes the leading dimension straight to cuBLAS, no copy needed.
            xb = xh.view(bs, _CHUNKS, k).transpose(0, 1)
            wb = self._wT_half.view(_CHUNKS, k, n)
            partials = torch.bmm(xb, wb)  # (C, bs, n) fp16, fp32 accumulation
            return _fused_op.chunked_partial_maxpool2_sum_scale(
                partials, b.detach(), float(self.scale_factor)
            )
        # Fallback (CPU / other dtypes / unsupported shapes): original ops.
        y = F.linear(x, w, b)
        y = F.max_pool1d(y.unsqueeze(1), self.kernel_size).squeeze(1)
        y = torch.sum(y, dim=1)
        return y * self.scale_factor
```
Result of evaluating it:
The solution is correct on the test inputs. Mean runtime 1.73 ms; the PyTorch reference (with TF32 enabled) takes 3.44 ms; speedup 1.988x.
Profiler, top device kernels of one forward pass of your solution:
| device kernel | total device time (us) | calls |
|---|---|---|
| ampere_fp16_s16816gemm_fp16_128x128_ldg8_f2f_stages_32x5_nn | 1618.5 | 1 |
| void chunked_partial_maxpool2_sum_scale_kernel<4>(__half const*, float const*, float*, int | 28.4 | 1 |
| void at::native::vectorized_elementwise_kernel<4, at::native::float16_copy_kernel_cuda(at: | 16.4 | 1 |

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.
