You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    A model that performs a 3D transposed convolution, followed by batch normalization, 
    two average pooling layers.
    """
    def __init__(self, in_channels, out_channels, kernel_size, stride, padding, bias_shape):
        super(Model, self).__init__()
        self.conv_transpose = nn.ConvTranspose3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)
        self.batch_norm = nn.BatchNorm3d(out_channels)
        self.avg_pool1 = nn.AvgPool3d(kernel_size=2)
        self.avg_pool2 = nn.AvgPool3d(kernel_size=2)

    def forward(self, x):
        x = self.conv_transpose(x)
        x = self.batch_norm(x)
        x = self.avg_pool1(x)
        x = self.avg_pool2(x)
        return x


batch_size = 64
in_channels = 3
out_channels = 16
depth, height, width = 32, 32, 32
kernel_size = 3
stride = 2
padding = 1
bias_shape = (out_channels, 1, 1, 1)

def get_inputs():
    return [torch.rand(batch_size, in_channels, depth, height, width)]

def get_init_inputs():
    return [in_channels, out_channels, kernel_size, stride, padding, bias_shape]
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 4 of 6 for this task. Your previous solution (turn 3) was:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# ---------------------------------------------------------------------------
# Algebra behind the fusion (convT k=3,s=2,p=1 -> BN -> avgpool2 -> avgpool2):
#
#   convT output p receives x[i]*W[k] iff p = 2*i + k - 1.
#   The two stride-2 avg pools (63 -> 31 -> 15, odd sizes) only read convT
#   outputs p in [0,59], and final[q] = (1/64) * sum_{d in [0,3]^3} y[4q+d].
#   Gathering those 64 terms yields a *valid* stride-2 kernel-3 convolution
#   on x[0..30] with an effective kernel E:
#       final[oc][q] = sum_ic sum_{j in [0,2]^3} E[oc][ic][j] * x[ic][2q+j]
#   BatchNorm is a per-channel affine map and commutes with the average pools,
#   so it folds into E (scale) and a conv bias (shift).  The whole pooled path
#   is therefore ONE cuDNN conv3d (TF32 tensor cores allowed).
#
#   Train-mode batch statistics of the *full* 63^3 convT output are computed
#   by a dedicated kernel that evaluates y on the fly (each output element
#   costs <= 8 taps x IC MACs, parity of p determines the taps) using a
#   shared-memory input tile + register-blocked x values, so the ~1 GB
#   intermediate tensor is never materialized.
# ---------------------------------------------------------------------------

cuda_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>

#define TILE_OUT 16
#define TILE_IN 9
#define NREG 5

// Build effective kernel E2[oc][ic][27] (scaled by BN) and shift[oc].
// Valid (d,j)->k mapping per dim: j=0 -> k={1,2}, j=1 -> k={0,1,2}, j=2 -> k={0}.
__global__ void build_params_kernel(const float* __restrict__ W,
                                    const float* __restrict__ bn_w,
                                    const float* __restrict__ bn_b,
                                    const float* __restrict__ mean,
                                    const float* __restrict__ var,
                                    const float* __restrict__ conv_bias,
                                    float* __restrict__ E2,
                                    float* __restrict__ shift,
                                    int IC, int OC, float eps) {
    int oc = blockIdx.x / IC;
    int ic = blockIdx.x % IC;
    int j  = threadIdx.x;
    if (j > 27) return;

    float scale = bn_w[oc] * rsqrtf(var[oc] + eps);
    if (threadIdx.x == 0)
        shift[oc] = bn_b[oc] + scale * (conv_bias[oc] - mean[oc]);
    if (j == 27) return;

    int jz = j / 9, jy = (j / 3) % 3, jx = j % 3;
    int kzl[3], kyl[3], kxl[3], nz, ny, nx;
    if (jz == 0)      { kzl[0]=1; kzl[1]=2; nz=2; }
    else if (jz == 1) { kzl[0]=0; kzl[1]=1; kzl[2]=2; nz=3; }
    else              { kzl[0]=0; nz=1; }
    if (jy == 0)      { kyl[0]=1; kyl[1]=2; ny=2; }
    else if (jy == 1) { kyl[0]=0; kyl[1]=1; kyl[2]=2; ny=3; }
    else              { kyl[0]=0; ny=1; }
    if (jx == 0)      { kxl[0]=1; kxl[1]=2; nx=2; }
    else if (jx == 1) { kxl[0]=0; kxl[1]=1; kxl[2]=2; nx=3; }
    else              { kxl[0]=0; nx=1; }

    const float* wb = W + ((long)ic * OC + oc) * 27;
    float acc = 0.f;
    for (int a = 0; a < nz; ++a)
        for (int b = 0; b < ny; ++b)
            for (int c = 0; c < nx; ++c)
                acc += wb[kzl[a] * 9 + kyl[b] * 3 + kxl[c]];
    E2[((long)oc * IC + ic) * 27 + j] = acc * (scale * (1.0f / 64.0f));
}

// On-the-fly batch statistics of the full convT output y (63^3 per slice).
// y[n][oc][p] = bias[oc] + sum_ic sum_{valid k} x[n][ic][i]*W[ic][oc][k],
// p = 2i + k - 1 per dim (p even: single tap k=1; p odd: taps k=0,2).
// Each block handles a 16x16x16 output tile for one batch element n and all
// output channels (x input tile 3*9*9*9 kept in shared memory, W in shared,
// inner x values register-blocked).  Per-block double partials are atomically
// accumulated per channel.  y itself is never written to memory.
__global__ void stats_kernel(const float* __restrict__ x,
                             const float* __restrict__ W,
                             const float* __restrict__ bias,
                             double* __restrict__ sum,
                             double* __restrict__ sumsq,
                             int IC, int OC, int XSZ) {
    __shared__ float xs[3 * TILE_IN * TILE_IN * TILE_IN];
    __shared__ float Ws[16 * 3 * 27];
    __shared__ double bs[16];
    __shared__ double bs2[16];

    const int tid  = threadIdx.x;
    const int n    = blockIdx.y;
    const int pz0  = blockIdx.x * TILE_OUT;          // 0, 16, 32, 48
    const int iz0  = (pz0 + 1) >> 1;
    const int zmax = min(63, pz0 + TILE_OUT);

    // load x tile [ic][dz][dy][dx] -> x[n][ic][iz0+dz][ty0+dy][tx0+dx]
    const long xn = (long)n * IC * XSZ * XSZ * XSZ;
    for (int idx = tid; idx < IC * 729; idx += 256) {
        int dx = idx % TILE_IN;
        int t  = idx / TILE_IN;
        int dy = t % TILE_IN;
        int dz = (t / TILE_IN) % TILE_IN;
        int ic = t / (TILE_IN * TILE_IN);
        xs[idx] = x[xn + ((long)ic * XSZ + (iz0 + dz)) * (XSZ * XSZ)
                    + (long)(ty0 + dy) * XSZ + (tx0 + dx)];
    }
    for (int idx = tid; idx < OC * IC * 27; idx += 256)
        Ws[idx] = W[idx];
    __syncthreads();

    double accS[16], accQ[16];
    #pragma unroll
    for (int c = 0; c < 16; ++c) { accS[c] = 0.0; accQ[c] = 0.0; }

    // parity of pz0 / ty0 / tx0 is even (multiples of 16 and 8)
    int kzmin = (pz0 == 0) ? 1 : 0;
    int kymax = (zmax == 63) ? 1 : 2;
    int kxmax = 2;

    const int r  = tid >> 6;          // 0..3  -> pz = pz0 + 2r + oz
    const int ty = (tid >> 4) & 3;    // 0..3
    const int tx = tid & 15;          // 0..15 -> covers 32 px in pairs
    const int pz_b = pz0 + 2 * r;
    const int py_b = ty0 + 2 * ty;
    const int px_b = tx0 + 2 * tx;
    const int izb = (pz_b + 1) >> 1;  // pz_b even -> (pz_b+2)/2
    const int iyb = (py_b + 1) >> 1;
    const int ixb = (px_b + 1) >> 1;

    for (int oz = 0; oz < 2; ++oz) {
        int pz = pz_b + oz;
        if (pz >= zmax) break;
        int kz0, kz1, dzbase;
        if (oz == 0) { kz0 = kzmin; kz1 = 2;     dzbase = izb - 1 - iz0; }
        else         { kz0 = 0;     kz1 = kzmax; dzbase = izb - iz0;     }
        for (int oy = 0; oy < 2; ++oy) {
            int ky0, ky1, dybase;
            if (oy == 0) { ky0 = 0; ky1 = 2;     dybase = iyb - 1 - ty0; }
            else         { ky0 = 0; ky1 = kymax; dybase = iyb - ty0;     }

            // load register-blocked x values: [dz][dy][5 dx][ic]
            float xr[2][2][NREG][3];
            #pragma unroll
            for (int a = 0; a < 2; ++a) {
                #pragma unroll
                for (int b = 0; b < 2; ++b) {
                    const float* xrow = xs + ((a * 2 + dzbase) * TILE_IN + (b * 2 + dybase)) * TILE_IN + (ixb - 1 - tx0);
                    #pragma unroll
                    for (int c = 0; c < NREG; ++c) {
                        #pragma unroll
                        for (int ic = 0; ic < 3; ++ic)
                            xr[a][b][c][ic] = xrow[ic * 729 + c];
                    }
                }
            }

            float y0[16], y1[16];
            #pragma unroll
            for (int c = 0; c < 16; ++c) {
                float bb = bias[c];
                y0[c] = bb; y1[c] = bb;
            }

            for (int ic = 0; ic < IC; ++ic) {
                #pragma unroll
                for (int a = 0; a < 2; ++a) {
                    #pragma unroll
                    for (int kz = kz0; kz <= kz1; ++kz) {
                        #pragma unroll
                        for (int b = 0; b < 2; ++b) {
                            #pragma unroll
                            for (int ky = ky0; ky <= ky1; ++ky) {
                                int wbase = ic * 27 + kz * 9 + ky * 3;
                                #pragma unroll
                                for (int c = 0; c < NREG; ++c) {
                                    float xv = xr[a][b][c][ic];
                                    #pragma unroll
                                    for (int kx = 0; kx <= kxmax; ++kx) {
                                        float w0 = Ws[wbase + kx];
                                        #pragma unroll
                                        for (int oc = 0; oc < 16; ++oc) {
                                            float w = Ws[oc * 81 + wbase + kx];
                                            if (kx == 2 - c) y1[oc] += xv * w;
                                            else             y0[oc] += xv * w;
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
            #pragma unroll
            for (int c = 0; c < 16; ++c) {
                accS[c] += (double)(y0[c] + y1[c]);
                accQ[c] += (double)(y0[c] * y0[c] + y1[c] * y1[c]);
            }
        }
    }

    for (int oc = 0; oc < OC; ++oc) {
        if (tid == 0) { bs[oc] = 0.0; bs2[oc] = 0.0; }
        __syncthreads();
        double vs = accS[oc], vq = accQ[oc];
        #pragma unroll
        for (int off = 16; off > 0; off >>= 1) {
            vs += __shfl_down_sync(0xffffffffu, vs, off);
            vq += __shfl_down_sync(0xffffffffu, vq, off);
        }
        if ((tid & 31) == 0) {
            atomicAdd(&bs[oc], vs);
            atomicAdd(&bs2[oc], vq);
        }
        __syncthreads();
        if (tid == 0) {
            atomicAdd(&sum[oc], bs[oc]);
            atomicAdd(&sumsq[oc], bs2[oc]);
        }
        __syncthreads();
    }
}

// zero the stats accumulators
__global__ void zero_stats_kernel(double* __restrict__ sum,
                                  double* __restrict__ sumsq, int C) {
    int c = blockIdx.x * blockDim.x + threadIdx.x;
    if (c < C) { sum[c] = 0.0; sumsq[c] = 0.0; }
}

// compute batch mean/var and update running stats like aten batch_norm
__global__ void bn_finalize_kernel(const double* __restrict__ sum,
                                   const double* __restrict__ sumsq,
                                   float* __restrict__ running_mean,
                                   float* __restrict__ running_var,
                                   float* __restrict__ out_mean,
                                   float* __restrict__ out_var,
                                   long count, double momentum, int C) {
    int c = blockIdx.x * blockDim.x + threadIdx.x;
    if (c >= C) return;
    double m  = sum[c] / (double)count;
    double sq = sumsq[c] / (double)count;
    double v  = sq - m * m;
    if (v < 0.0) v = 0.0;
    out_mean[c] = (float)m;
    out_var[c]  = (float)v;
    double unb = (count > 1) ? v * ((double)count / (double)(count - 1)) : 0.0;
    running_mean[c] = (float)((1.0 - momentum) * (double)running_mean[c] + momentum * m);
    running_var[c]  = (float)((1.0 - momentum) * (double)running_var[c]  + momentum * unb);
}

torch::Tensor build_params(torch::Tensor W, torch::Tensor bn_w, torch::Tensor bn_b,
                           torch::Tensor mean, torch::Tensor var, torch::Tensor conv_bias,
                           int64_t IC, int64_t OC, double eps) {
    auto E2    = torch::empty({OC, IC, 3, 3, 3}, W.options());
    auto shift = torch::empty({OC}, W.options());
    auto stream = at::cuda::getCurrentCUDAStream();
    dim3 grid((unsigned)(OC * IC));
    build_params_kernel<<<grid, 32, 0, stream>>>(
        W.data_ptr<float>(), bn_w.data_ptr<float>(), bn_b.data_ptr<float>(),
        mean.data_ptr<float>(), var.data_ptr<float>(), conv_bias.data_ptr<float>(),
        E2.data_ptr<float>(), shift.data_ptr<float>(), (int)IC, (int)OC, (float)eps);
    return torch::cat({E2.reshape({OC, -1}), shift.reshape({OC, 1})}, 1);
}

// train-mode: on-the-fly convT batch stats -> batch mean/var (+running update)
std::vector<torch::Tensor> stats_train(torch::Tensor x, torch::Tensor W, torch::Tensor conv_bias,
                                       torch::Tensor running_mean, torch::Tensor running_var,
                                       int64_t N, int64_t IC, int64_t OC,
                                       double momentum, int64_t XSZ) {
    auto stream = at::cuda::getCurrentCUDAStream();
    auto opts_d = torch::TensorOptions().dtype(torch::kFloat64).device(x.device());
    auto sum   = torch::empty({OC}, opts_d);
    auto sumsq = torch::empty({OC}, opts_d);

    zero_stats_kernel<<<1, 64, 0, stream>>>(sum.data_ptr<double>(), sumsq.data_ptr<double>(), (int)OC);

    dim3 sgrid(4, (unsigned)N, 1);
    stats_kernel<<<sgrid, 256, 0, stream>>>(
        x.data_ptr<float>(), W.data_ptr<float>(), conv_bias.data_ptr<float>(),
        sum.data_ptr<double>(), sumsq.data_ptr<double>(), (int)IC, (int)OC, (int)XSZ);

    auto bmean = torch::empty({OC}, x.options());
    auto bvar  = torch::empty({OC}, x.options());
    long count = (long)N * 250047;   // 63*63*63
    bn_finalize_kernel<<<1, 64, 0, stream>>>(
        sum.data_ptr<double>(), sumsq.data_ptr<double>(),
        running_mean.data_ptr<float>(), running_var.data_ptr<float>(),
        bmean.data_ptr<float>(), bvar.data_ptr<float>(),
        count, momentum, (int)OC);
    return {bmean, bvar};
}
"""

cpp_source = r"""
torch::Tensor build_params(torch::Tensor W, torch::Tensor bn_w, torch::Tensor bn_b,
                           torch::Tensor mean, torch::Tensor var, torch::Tensor conv_bias,
                           int64_t IC, int64_t OC, double eps);
std::vector<torch::Tensor> stats_train(torch::Tensor x, torch::Tensor W, torch::Tensor conv_bias,
                                       torch::Tensor running_mean, torch::Tensor running_var,
                                       int64_t N, int64_t IC, int64_t OC,
                                       double momentum, int64_t XSZ);
"""

_fused = load_inline(
    name="fused_convT_bn_avgpool_v3",
    cpp_sources=cpp_source,
    cuda_sources=cuda_source,
    functions=["build_params", "stats_train"],
    verbose=False,
    extra_cuda_cflags=["-O3", "--use_fast_math"],
)


class ModelNew(nn.Module):
    """
    Optimized version of Model.  The conv-transpose (k=3, s=2, p=1), batch-norm
    and both 2x2x2 average pools are collapsed algebraically into a single
    valid stride-2 kernel-3 convolution with an effective kernel (BN folded
    into its weights/bias), executed with one cuDNN conv3d.  In training mode
    the batch statistics of the transposed-conv output are computed on the fly
    by a custom CUDA kernel (the 63^3-per-channel intermediate is never
    materialized), removing the dominant cuDNN dgrad + memset + stats passes.
    """

    def __init__(self, in_channels, out_channels, kernel_size, stride, padding, bias_shape):
        super(ModelNew, self).__init__()
        self.conv_transpose = nn.ConvTranspose3d(
            in_channels, out_channels, kernel_size, stride=stride, padding=padding
        )
        self.batch_norm = nn.BatchNorm3d(out_channels)
        self._in_channels = in_channels
        self._out_channels = out_channels

    def _fallback(self, x):
        x = self.conv_transpose(x)
        x = self.batch_norm(x)
        x = F.avg_pool3d(x, kernel_size=2)
        x = F.avg_pool3d(x, kernel_size=2)
        return x

    def forward(self, x):
        ic, oc = self._in_channels, self._out_channels
        bn = self.batch_norm
        ct = self.conv_transpose

        fast_ok = (
            x.is_cuda and x.dtype == torch.float32 and x.dim() == 5
            and x.size(1) == ic and x.size(2) == 32 and x.size(3) == 32 and x.size(4) == 32
            and ic == 3 and oc == 16
            and ct.bias is not None and bn.affine and bn.track_running_stats
        )
        if not fast_ok:
            return self._fallback(x)

        x = x.contiguous()
        w = ct.weight.contiguous()
        conv_bias = ct.bias.contiguous()
        N = x.shape[0]

        if self.training:
            bmean, bvar = _fused.stats_train(
                x, w, conv_bias, bn.running_mean, bn.running_var,
                N, ic, oc, float(bn.momentum), 32,
            )
            mean_t, var_t = bmean, bvar
        else:
            mean_t = bn.running_mean
            var_t = bn.running_var

        params = _fused.build_params(
            w, bn.weight.contiguous(), bn.bias.contiguous(),
            mean_t, var_t, conv_bias, ic, oc, float(bn.eps),
        )
        E2 = params[:, : ic * 27].reshape(oc, ic, 3, 3, 3)
        shift = params[:, ic * 27]
        return F.conv3d(x, E2, shift, stride=2)


batch_size = 64
in_channels = 3
out_channels = 16
depth, height, width = 32, 32, 32
kernel_size = 3
stride = 2
padding = 1
bias_shape = (out_channels, 1, 1, 1)


def get_inputs():
    return [torch.rand(batch_size, in_channels, depth, height, width)]


def get_init_inputs():
    return [in_channels, out_channels, kernel_size, stride, padding, bias_shape]
```
Result of evaluating it:
The solution failed to compile. Error output:
```
RuntimeError: Error building extension 'fused_convT_bn_avgpool_v3': [1/3] /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/bin/nvcc -MD -MF cuda.cuda.o.d -DTORCH_EXTENSION_NAME=fused_convT_bn_avgpool_v3 -DTORCH_API_INCLUDE_EXTENSION_H -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include/torch/csrc/api/include -isystem /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/include -isystem /usr/include/python3.12 -D__CUDA_NO_HALF_OPERATORS__ -D__CUDA_NO_HALF_CONVERSIONS__ -D__CUDA_NO_BFLOAT16_CONVERSIONS__ -D__CUDA_NO_HALF2_OPERATORS__ --expt-relaxed-constexpr -gencode=arch=compute_80,code=sm_80 --compiler-options '-fPIC' -O3 --use_fast_math -std=c++20 -c /srv/jobs/1791687059121201662-526805-0/build/fused_convT_bn_avgpool_v3/cuda.cu -o cuda.cuda.o 
FAILED: [code=2] cuda.cuda.o 
/opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/bin/nvcc -MD -MF cuda.cuda.o.d -DTORCH_EXTENSION_NAME=fused_convT_bn_avgpool_v3 -DTORCH_API_INCLUDE_EXTENSION_H -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include/torch/csrc/api/include -isystem /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/include -isystem /usr/include/python3.12 -D__CUDA_NO_HALF_OPERATORS__ -D__CUDA_NO_HALF_CONVERSIONS__ -D__CUDA_NO_BFLOAT16_CONVERSIONS__ -D__CUDA_NO_HALF2_OPERATORS__ --expt-relaxed-constexpr -gencode=arch=compute_80,code=sm_80 --compiler-options '-fPIC' -O3 --use_fast_math -std=c++20 -c /srv/jobs/1791687059121201662-526805-0/build/fused_convT_bn_avgpool_v3/cuda.cu -o cuda.cuda.o 
/srv/jobs/1791687059121201662-526805-0/build/fused_convT_bn_avgpool_v3/cuda.cu(88): error: identifier "ty0" is undefined
                      + (long)(ty0 + dy) * XSZ + (tx0 + dx)];
                               ^

/srv/jobs/1791687059121201662-526805-0/build/fused_convT_bn_avgpool_v3/cuda.cu(88): error: identifier "tx0" is undefined
                      + (long)(ty0 + dy) * XSZ + (tx0 + dx)];
                                                  ^

/srv/jobs/1791687059121201662-526805-0/build/fused_convT_bn_avgpool_v3/cuda.cu(107): error: identifier "ty0" is undefined
      const int py_b = ty0 + 2 * ty;
                       ^

/srv/jobs/1791687059121201662-526805-0/build/fused_convT_bn_avgpool_v3/cuda.cu(108): error: identifier "tx0" is undefined
      const int px_b = tx0 + 2 * tx;
                       ^

/srv/jobs/1791687059121201662-526805-0/build/fused_convT_bn_avgpool_v3/cuda.cu(118): error: identifier "kzmax" is undefined
          else { kz0 = 0; kz1 = kzmax; dzbase = izb - iz0; }
                                ^

5 errors detected in the compilation of "/srv/jobs/1791687059121201662-526805-0/build/fused_convT_bn_avgpool_v3/cuda.cu".
[2/3] c++ -MMD -MF main.o.d -DTORCH_EXTENSION_NAME=fused_convT_bn_avgpool_v3 -DTORCH_API_INCLUDE_EXTENSION_H -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include/torch/csrc/api/include -isystem /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/include -isystem /usr/include/python3.12 -fPIC -std=c++20 -c /srv/jobs/1791687059121201662-526805-0/build/fused_convT_bn_avgpool_v3/main.cpp -o main.o 
ninja: build stopped: subcommand failed.

```

The fastest correct solution so far (9.654x speedup) is:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# ---------------------------------------------------------------------------
# Math behind the fusion (kernel_size=3, stride=2, padding=1 transposed conv,
# followed by two stride-2 2x2x2 average pools):
#
#   convT output p receives x[i] with weight W[k] iff p = 2*i + k - 1.
#   Two avg pools with odd sizes (63 -> 31 -> 15) only use convT outputs
#   p in [0,59] per dim, i.e. final[q] = (1/64) * sum_{d in [0,3]^3} y[4q+d].
#   Gathering the 64 sub-terms gives a *valid* stride-2 kernel-3 convolution
#   on x[0..30] with an "effective" kernel E:
#       final[oc][q] = sum_ic sum_{j in [0,2]^3} E[oc][ic][j] * x[ic][2q+j]
#   where E folds W over the 64 pooled positions (and the 1/64 factor).
#   BatchNorm is per-channel affine, so it commutes with the average pool and
#   collapses into a per-channel scale/shift applied at the end.
#
# Train mode: batch statistics of the *full* convT output are computed by a
# dedicated kernel that evaluates y = convT(x) on the fly (each output element
# costs <= 8 taps x IC MACs; parity of p determines the taps) and accumulates
# per-channel sum / sum-of-squares directly in registers + shared memory, so
# the 1 GB intermediate tensor is never materialized.
# ---------------------------------------------------------------------------

cuda_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>

#define ROWS 8
#define TOTAL_ROWS 225
#define X_TILE_FLOATS (ROWS * 3 * 3 * 3 * 31)
#define SLICE_ELEMS 250047   // 63*63*63

// Build effective kernel E[oc][ic][27] from conv-transpose W[ic][oc][27].
// Valid (d,j)->k mapping per dim: j=0 -> k={1,2}, j=1 -> k={0,1,2}, j=2 -> k={0}.
__global__ void build_eff_kernel(const float* __restrict__ W,
                                 float* __restrict__ E,
                                 int IC, int OC) {
    int oc = blockIdx.x / IC;
    int ic = blockIdx.x % IC;
    int j = threadIdx.x;              // 0..26
    if (j >= 27) return;
    int jz = j / 9, jy = (j / 3) % 3, jx = j % 3;

    int kzl[3], kyl[3], kxl[3], nz, ny, nx;
    if (jz == 0)      { kzl[0]=1; kzl[1]=2; nz=2; }
    else if (jz == 1) { kzl[0]=0; kzl[1]=1; kzl[2]=2; nz=3; }
    else              { kzl[0]=0; nz=1; }
    if (jy == 0)      { kyl[0]=1; kyl[1]=2; ny=2; }
    else if (jy == 1) { kyl[0]=0; kyl[1]=1; kyl[2]=2; ny=3; }
    else              { kyl[0]=0; ny=1; }
    if (jx == 0)      { kxl[0]=1; kxl[1]=2; nx=2; }
    else if (jx == 1) { kxl[0]=0; kxl[1]=1; kxl[2]=2; nx=3; }
    else              { kxl[0]=0; nx=1; }

    const float* wb = W + ((long)ic * OC + oc) * 27;
    float acc = 0.f;
    for (int a = 0; a < nz; ++a)
        for (int b = 0; b < ny; ++b)
            for (int c = 0; c < nx; ++c)
                acc += wb[kzl[a] * 9 + kyl[b] * 3 + kxl[c]];
    E[((long)oc * IC + ic) * 27 + j] = acc * (1.0f / 64.0f);
}

// Fully fused: effective stride-2 conv + BN affine + both avg pools.
// x: [N][IC][32][32][32], E: [OC][IC][27], out: [N][OC][15][15][15]
__global__ void fused_conv_bn_pool_kernel(
        const float* __restrict__ x,
        const float* __restrict__ E,
        const float* __restrict__ bn_w,
        const float* __restrict__ bn_b,
        const float* __restrict__ bn_mean,   // running_mean (eval) or batch mean (train)
        const float* __restrict__ bn_var,    // running_var  (eval) or batch biased var (train)
        const float* __restrict__ conv_bias,
        float* __restrict__ out,
        int N, int IC, int OC, float eps) {
    __shared__ float xs[X_TILE_FLOATS];
    __shared__ float Es[16 * 3 * 27];

    const int n   = blockIdx.z;
    const int row = blockIdx.x * ROWS + (threadIdx.x >> 4);  // 0..224
    const int qx  = threadIdx.x & 15;
    const int tid = threadIdx.x;

    // load effective kernel
    for (int i = tid; i < OC * IC * 27; i += blockDim.x)
        Es[i] = E[i];

    // load input tile: rows of this block -> x[n][ic][2qz+dz][2qy+dy][0..30]
    const int row0 = blockIdx.x * ROWS;
    const int nrows = min(ROWS, TOTAL_ROWS - row0);
    const long xbase = (long)n * IC * 32768;
    for (int idx = tid; idx < nrows * 3 * 3 * 3 * 31; idx += blockDim.x) {
        int xx  = idx % 31;
        int t   = idx / 31;
        int dy  = t % 3;
        int t2  = t / 3;
        int dz  = t2 % 3;
        int ic  = t2 / 3;
        int r   = ic / 3;  ic = ic % 3;
        int qz  = (row0 + r) / 15;
        int qy  = (row0 + r) % 15;
        int gz  = 2 * qz + dz;
        int gy  = 2 * qy + dy;
        xs[idx] = x[xbase + ((long)ic * 32 + gz) * 1024 + gy * 32 + xx];
    }
    __syncthreads();

    if (qx >= 15 || row >= TOTAL_ROWS) return;
    const int qz = row / 15;
    const int qy = row % 15;
    const int r  = threadIdx.x >> 4;

    for (int oc = 0; oc < OC; ++oc) {
        const float* ep = Es + oc * IC * 27;
        float acc = 0.f;
        for (int ic = 0; ic < IC; ++ic) {
            const float* xp = xs + ((r * 3 + ic) * 9) * 31 + 2 * qx;
            #pragma unroll
            for (int j = 0; j < 27; ++j) {
                int jz = j / 9, jy = (j / 3) % 3, jx = j % 3;
                acc += ep[j] * xp[(jz * 3 + jy) * 31 + jx];
            }
            ep += 27;
        }
        float scale = bn_w[oc] * rsqrtf(bn_var[oc] + eps);
        float shift = bn_b[oc] + scale * (conv_bias[oc] - bn_mean[oc]);
        out[(((long)n * OC + oc) * 225 + row) * 15 + qx] = acc * scale + shift;
    }
}

// Train-mode batch statistics of the full convT output y (63^3 per slice),
// computed on the fly: y is never written to global memory.
//   y[n][oc][pz][py][px] = bias[oc]
//       + sum_ic sum_{valid k taps} x[n][ic][iz][iy][ix] * W[ic][oc][k]
// For each dim: p even -> single tap (k=1, i=p/2);
//               p odd  -> two taps (k=0, i=(p+1)/2) and (k=2, i=(p-1)/2).
// block = (64, 4) threads -> px = threadIdx.x, py = blockIdx.x*4 + threadIdx.y,
// loop over pz.  Per-block partial sums are reduced in shared memory and
// atomically accumulated per output channel.
__global__ void convt_stats_kernel(const float* __restrict__ x,
                                   const float* __restrict__ W,
                                   const float* __restrict__ bias,
                                   double* __restrict__ sum,
                                   double* __restrict__ sumsq,
                                   int IC, int OC) {
    __shared__ float Ws[8 * 27];
    __shared__ double bs[256];
    __shared__ double bs2[256];

    const int oc  = blockIdx.z;
    const int n   = blockIdx.y;
    const int tid = threadIdx.x + threadIdx.y * blockDim.x;

    for (int i = tid; i < IC * 27; i += 256) {
        int ic = i / 27, k = i - ic * 27;
        Ws[i] = W[((long)ic * OC + oc) * 27 + k];
    }
    __syncthreads();

    const int px = threadIdx.x;
    const int py = blockIdx.x * 4 + threadIdx.y;

    double s = 0.0, s2 = 0.0;
    if (px < 63 && py < 63) {
        int ix[2], kx[2], iy[2], ky[2], nx, ny;
        if (px & 1) { ix[0]=(px+1)>>1; kx[0]=0; ix[1]=(px-1)>>1; kx[1]=2; nx=2; }
        else        { ix[0]=px>>1;     kx[0]=1;                       nx=1; }
        if (py & 1) { iy[0]=(py+1)>>1; ky[0]=0; iy[1]=(py-1)>>1; ky[1]=2; ny=2; }
        else        { iy[0]=py>>1;     ky[0]=1;                       ny=1; }

        const float b = bias[oc];
        const long xn = (long)n * IC * 32768;

        for (int pz = 0; pz < 63; ++pz) {
            int iz[2], kz[2], nz;
            if (pz & 1) { iz[0]=(pz+1)>>1; kz[0]=0; iz[1]=(pz-1)>>1; kz[1]=2; nz=2; }
            else        { iz[0]=pz>>1;     kz[0]=1;                       nz=1; }

            float acc = b;
            for (int ic = 0; ic < IC; ++ic) {
                const float* xp = x + xn + (long)ic * 32768;
                const float* wp = Ws + ic * 27;
                for (int a = 0; a < nz; ++a) {
                    const float* xz = xp + (long)iz[a] * 1024;
                    const int kza = kz[a] * 9;
                    for (int bb = 0; bb < ny; ++bb) {
                        const float* xy = xz + iy[bb] * 32;
                        const int kb = kza + ky[bb] * 3;
                        #pragma unroll
                        for (int c = 0; c < 2; ++c) {
                            if (c < nx) acc += xy[ix[c]] * wp[kb + kx[c]];
                        }
                    }
                }
            }
            s  += (double)acc;
            s2 += (double)acc * (double)acc;
        }
    }

    bs[tid] = s; bs2[tid] = s2;
    __syncthreads();
    for (int off = 128; off > 0; off >>= 1) {
        if (tid < off) {
            bs[tid]  += bs[tid + off];
            bs2[tid] += bs2[tid + off];
        }
        __syncthreads();
    }
    if (tid == 0) {
        atomicAdd(&sum[oc], bs[0]);
        atomicAdd(&sumsq[oc], bs2[0]);
    }
}

// compute batch mean/var and update running stats like aten batch_norm
__global__ void bn_finalize_kernel(const double* __restrict__ sum,
                                   const double* __restrict__ sumsq,
                                   float* __restrict__ running_mean,
                                   float* __restrict__ running_var,
                                   float* __restrict__ out_mean,
                                   float* __restrict__ out_var,
                                   long count, double momentum, float eps, int C) {
    int c = blockIdx.x * blockDim.x + threadIdx.x;
    if (c >= C) return;
    double m  = sum[c] / (double)count;
    double sq = sumsq[c] / (double)count;
    double v  = sq - m * m;
    if (v < 0.0) v = 0.0;
    out_mean[c] = (float)m;
    out_var[c]  = (float)v;
    double unb = (count > 1) ? v * ((double)count / (double)(count - 1)) : 0.0;
    running_mean[c] = (float)((1.0 - momentum) * (double)running_mean[c] + momentum * m);
    running_var[c]  = (float)((1.0 - momentum) * (double)running_var[c]  + momentum * unb);
}

torch::Tensor build_eff(torch::Tensor W, int64_t IC, int64_t OC) {
    auto E = torch::empty({OC, IC, 27}, W.options());
    auto stream = at::cuda::getCurrentCUDAStream();
    dim3 grid(OC * IC);
    build_eff_kernel<<<grid, 32, 0, stream>>>(W.data_ptr<float>(), E.data_ptr<float>(), (int)IC, (int)OC);
    return E;
}

torch::Tensor fused_eval(torch::Tensor x, torch::Tensor E,
                         torch::Tensor bn_w, torch::Tensor bn_b,
                         torch::Tensor bn_mean, torch::Tensor bn_var,
                         torch::Tensor conv_bias,
                         int64_t N, int64_t IC, int64_t OC, double eps) {
    auto out = torch::empty({N, OC, 15, 15, 15}, x.options());
    auto stream = at::cuda::getCurrentCUDAStream();
    dim3 grid((TOTAL_ROWS + ROWS - 1) / ROWS, 1, N);
    fused_conv_bn_pool_kernel<<<grid, 128, 0, stream>>>(
        x.data_ptr<float>(), E.data_ptr<float>(),
        bn_w.data_ptr<float>(), bn_b.data_ptr<float>(),
        bn_mean.data_ptr<float>(), bn_var.data_ptr<float>(),
        conv_bias.data_ptr<float>(), out.data_ptr<float>(),
        (int)N, (int)IC, (int)OC, (float)eps);
    return out;
}

// train-mode: on-the-fly convT batch stats (y never materialized),
// then fused effective-conv + BN + pools with the batch stats.
torch::Tensor fused_train(torch::Tensor x, torch::Tensor E, torch::Tensor W,
                          torch::Tensor bn_w, torch::Tensor bn_b,
                          torch::Tensor running_mean, torch::Tensor running_var,
                          torch::Tensor conv_bias,
                          int64_t N, int64_t IC, int64_t OC,
                          double eps, double momentum) {
    auto stream = at::cuda::getCurrentCUDAStream();
    auto opts_d = torch::TensorOptions().dtype(torch::kFloat64).device(x.device());
    auto sum    = torch::zeros({OC}, opts_d);
    auto sumsq  = torch::zeros({OC}, opts_d);

    dim3 sgrid(16, (unsigned)N, (unsigned)OC);
    dim3 sblock(64, 4);
    convt_stats_kernel<<<sgrid, sblock, 0, stream>>>(
        x.data_ptr<float>(), W.data_ptr<float>(), conv_bias.data_ptr<float>(),
        sum.data_ptr<double>(), sumsq.data_ptr<double>(), (int)IC, (int)OC);

    auto bmean = torch::empty({OC}, x.options());
    auto bvar  = torch::empty({OC}, x.options());
    long count = (long)N * SLICE_ELEMS;
    bn_finalize_kernel<<<(unsigned)((OC + 63) / 64), 64, 0, stream>>>(
        sum.data_ptr<double>(), sumsq.data_ptr<double>(),
        running_mean.data_ptr<float>(), running_var.data_ptr<float>(),
        bmean.data_ptr<float>(), bvar.data_ptr<float>(),
        count, momentum, (float)eps, (int)OC);

    auto out = torch::empty({N, OC, 15, 15, 15}, x.options());
    dim3 grid((TOTAL_ROWS + ROWS - 1) / ROWS, 1, N);
    fused_conv_bn_pool_kernel<<<grid, 128, 0, stream>>>(
        x.data_ptr<float>(), E.data_ptr<float>(),
        bn_w.data_ptr<float>(), bn_b.data_ptr<float>(),
        bmean.data_ptr<float>(), bvar.data_ptr<float>(),
        conv_bias.data_ptr<float>(), out.data_ptr<float>(),
        (int)N, (int)IC, (int)OC, (float)eps);
    return out;
}
"""

cpp_source = r"""
torch::Tensor build_eff(torch::Tensor W, int64_t IC, int64_t OC);
torch::Tensor fused_eval(torch::Tensor x, torch::Tensor E,
                         torch::Tensor bn_w, torch::Tensor bn_b,
                         torch::Tensor bn_mean, torch::Tensor bn_var,
                         torch::Tensor conv_bias,
                         int64_t N, int64_t IC, int64_t OC, double eps);
torch::Tensor fused_train(torch::Tensor x, torch::Tensor E, torch::Tensor W,
                          torch::Tensor bn_w, torch::Tensor bn_b,
                          torch::Tensor running_mean, torch::Tensor running_var,
                          torch::Tensor conv_bias,
                          int64_t N, int64_t IC, int64_t OC,
                          double eps, double momentum);
"""

_fused = load_inline(
    name="fused_convT_bn_avgpool_v2",
    cpp_sources=cpp_source,
    cuda_sources=cuda_source,
    functions=["build_eff", "fused_eval", "fused_train"],
    verbose=False,
    extra_cuda_cflags=["-O3", "--use_fast_math"],
)


class ModelNew(nn.Module):
    """
    Optimized version of Model.  The conv-transpose (k=3, s=2, p=1), batch-norm
    and both 2x2x2 average pools are fused into custom CUDA kernels by
    algebraically collapsing the whole chain into one valid stride-2 kernel-3
    convolution with an effective kernel, plus a per-channel affine transform.
    In training mode the batch statistics of the transposed-conv output are
    computed on the fly (the 63^3-per-channel intermediate is never
    materialized), which removes the dominant cuDNN dgrad + memset + stats
    passes entirely.
    """

    def __init__(self, in_channels, out_channels, kernel_size, stride, padding, bias_shape):
        super(ModelNew, self).__init__()
        self.conv_transpose = nn.ConvTranspose3d(
            in_channels, out_channels, kernel_size, stride=stride, padding=padding
        )
        self.batch_norm = nn.BatchNorm3d(out_channels)
        self._in_channels = in_channels
        self._out_channels = out_channels

    def _fallback(self, x):
        x = self.conv_transpose(x)
        x = self.batch_norm(x)
        x = F.avg_pool3d(x, kernel_size=2)
        x = F.avg_pool3d(x, kernel_size=2)
        return x

    def forward(self, x):
        ic, oc = self._in_channels, self._out_channels
        bn = self.batch_norm
        ct = self.conv_transpose

        fast_ok = (
            x.is_cuda and x.dtype == torch.float32 and x.dim() == 5
            and x.size(1) == ic and x.size(2) == 32 and x.size(3) == 32 and x.size(4) == 32
            and ic == 3 and oc == 16
            and ct.bias is not None and bn.affine and bn.track_running_stats
        )
        if not fast_ok:
            return self._fallback(x)

        x = x.contiguous()
        w = ct.weight.contiguous()
        conv_bias = ct.bias.contiguous()
        N = x.shape[0]
        E = _fused.build_eff(w, ic, oc)

        if not self.training:
            return _fused.fused_eval(
                x, E,
                bn.weight.contiguous(), bn.bias.contiguous(),
                bn.running_mean.contiguous(), bn.running_var.contiguous(),
                conv_bias, N, ic, oc, float(bn.eps),
            )
        else:
            return _fused.fused_train(
                x, E, w,
                bn.weight.contiguous(), bn.bias.contiguous(),
                bn.running_mean, bn.running_var,
                conv_bias, N, ic, oc, float(bn.eps), float(bn.momentum),
            )


batch_size = 64
in_channels = 3
out_channels = 16
depth, height, width = 32, 32, 32
kernel_size = 3
stride = 2
padding = 1
bias_shape = (out_channels, 1, 1, 1)


def get_inputs():
    return [torch.rand(batch_size, in_channels, depth, height, width)]


def get_init_inputs():
    return [in_channels, out_channels, kernel_size, stride, padding, bias_shape]
```

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.


Precision rule: the timed forward must compute in FP32 (TF32 tensor-core math is allowed, as in the PyTorch reference). Do not cast inputs, weights or intermediate results to float16 or bfloat16 and do not call half-precision kernels in forward().
