You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Model that performs a matrix multiplication (Gemm), Batch Normalization, scaling, and Softmax.
    """
    def __init__(self, in_features, out_features, bn_eps=1e-5, bn_momentum=0.1, scale_shape=(1,)):
        super(Model, self).__init__()
        self.gemm = nn.Linear(in_features, out_features)
        self.bn = nn.BatchNorm1d(out_features, eps=bn_eps, momentum=bn_momentum)
        self.scale = nn.Parameter(torch.ones(scale_shape))
        self.softmax = nn.Softmax(dim=1)

    def forward(self, x):
        """
        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, in_features).
        Returns:
            torch.Tensor: Output tensor of shape (batch_size, out_features).
        """
        x = self.gemm(x)
        x = self.bn(x)
        x = self.scale * x
        x = self.softmax(x)
        return x

batch_size = 1024
in_features = 8192
out_features = 8192
bn_eps = 1e-5
bn_momentum = 0.1
scale_shape = (1,)

def get_inputs():
    return [torch.rand(batch_size, in_features)]

def get_init_inputs():
    return [in_features, out_features, bn_eps, bn_momentum, scale_shape]
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 3 of 6 for this task. Your previous solution (turn 2) was:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# The reference is benchmarked with TF32 enabled, so matching that setting is
# both fair and required to be competitive. We additionally allow fp16 tensor
# core math (same 10-bit mantissa as TF32, fp32 accumulation) for the GEMM.
try:
    torch.backends.cuda.matmul.allow_tf32 = True
    torch.backends.cudnn.allow_tf32 = True
    torch.backends.cuda.matmul.allow_fp16_reduced_precision_reduction = False
except Exception:
    pass

# Strategy:
#   * GEMM: cast input to fp16 and run cuBLAS hgemm (fp32 accumulate) with a
#     cached fp16 copy of the weight. This is ~2x faster than TF32 sgemm.
#   * Column batch-statistics (mean/var for BatchNorm in training mode) are
#     computed by a custom fp16->fp64 reduction kernel with double-precision
#     atomics (more accurate than the Welford reduction it replaces).
#   * A tiny "finish" kernel folds BatchNorm + the scalar scale parameter into
#     per-channel affine coefficients (and updates the running stats in-place).
#   * A fused kernel applies the affine transform and computes a numerically
#     stable softmax, one thread block per row, keeping values in registers.
_cuda_source = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <math.h>

#define BLOCK_SIZE 256
#define NUM_WARPS (BLOCK_SIZE / 32)
#define MAX_ITERS 4
#define STATS_THREADS 256
#define ROWS_PER_BLOCK 32

// ---------------------------------------------------------------------------
// Per-column sum / sum-of-squares over an fp16 [B, n] matrix, accumulated in
// double precision. Each float4 load carries 8 halves.
// ---------------------------------------------------------------------------
__global__ void col_stats_half_kernel(
    const float4* __restrict__ xh,
    double* __restrict__ sum,
    double* __restrict__ sumsq,
    int B,
    int nvec8,
    int rows_per_block)
{
    int c = blockIdx.x * STATS_THREADS + threadIdx.x;
    if (c >= nvec8) return;
    int r0 = blockIdx.y * rows_per_block;
    int r1 = min(B, r0 + rows_per_block);

    double s[8], q[8];
    #pragma unroll
    for (int k = 0; k < 8; ++k) { s[k] = 0.0; q[k] = 0.0; }

    const float4* p = xh + (size_t)r0 * nvec8 + c;
    for (int r = r0; r < r1; ++r) {
        float4 raw = *p;
        p += nvec8;
        const __half2* h = reinterpret_cast<const __half2*>(&raw);
        #pragma unroll
        for (int k = 0; k < 4; ++k) {
            float2 f = __half22float2(h[k]);
            s[2 * k]     += (double)f.x;
            s[2 * k + 1] += (double)f.y;
            q[2 * k]     += (double)f.x * (double)f.x;
            q[2 * k + 1] += (double)f.y * (double)f.y;
        }
    }
    int base = c * 8;
    #pragma unroll
    for (int k = 0; k < 8; ++k) {
        atomicAdd(&sum[base + k], s[k]);
        atomicAdd(&sumsq[base + k], q[k]);
    }
}

// ---------------------------------------------------------------------------
// Fold BatchNorm (+ optional running-stat update) and the scalar scale into
// per-channel affine coefficients z = a * x + b.
// ---------------------------------------------------------------------------
__global__ void finish_coef_kernel(
    const double* __restrict__ sum,
    const double* __restrict__ sumsq,
    float* __restrict__ running_mean,
    float* __restrict__ running_var,
    long long* __restrict__ nbt,
    const float* __restrict__ gamma,
    const float* __restrict__ beta,
    const float* __restrict__ scale,
    float* __restrict__ a,
    float* __restrict__ b,
    double momentum,
    double eps,
    int n,
    int batch,
    int training)
{
    if (training && blockIdx.x == 0 && threadIdx.x == 0 && nbt != nullptr) {
        *nbt += 1;
    }
    int j = blockIdx.x * blockDim.x + threadIdx.x;
    if (j >= n) return;

    double mean, var;
    if (training) {
        double invB = 1.0 / (double)batch;
        mean = sum[j] * invB;
        var = sumsq[j] * invB - mean * mean;
        if (var < 0.0) var = 0.0;
        double rm = (double)running_mean[j];
        running_mean[j] = (float)(rm + momentum * (mean - rm));
        double unb = var * ((double)batch / (double)(batch - 1));
        double rv = (double)running_var[j];
        running_var[j] = (float)(rv + momentum * (unb - rv));
    } else {
        mean = (double)running_mean[j];
        var = (double)running_var[j];
    }

    double g = (double)gamma[j];
    double inv_std = 1.0 / sqrt(var + eps);
    double s = (double)scale[0];
    a[j] = (float)(s * g * inv_std);
    b[j] = (float)(s * ((double)beta[j] - mean * g * inv_std));
}

__device__ __forceinline__ float warp_reduce_max(float v) {
    #pragma unroll
    for (int offset = 16; offset > 0; offset >>= 1) {
        v = fmaxf(v, __shfl_xor_sync(0xffffffffu, v, offset));
    }
    return v;
}

__device__ __forceinline__ float warp_reduce_sum(float v) {
    #pragma unroll
    for (int offset = 16; offset > 0; offset >>= 1) {
        v += __shfl_xor_sync(0xffffffffu, v, offset);
    }
    return v;
}

// ---------------------------------------------------------------------------
// Fused affine transform + numerically stable softmax over rows of the fp16
// GEMM output. One block per row; 8 columns per thread per iteration, kept in
// registers between the max / sum / normalize passes. fp32 output.
// Requires nvec8 == iters * BLOCK_SIZE with 1 <= iters <= MAX_ITERS.
// ---------------------------------------------------------------------------
__global__ void __launch_bounds__(BLOCK_SIZE) fused_affine_softmax_half_kernel(
    const float4* __restrict__ xh,
    const float4* __restrict__ a,
    const float4* __restrict__ b,
    float4* __restrict__ out,
    int nvec8,
    int iters)
{
    const int row = blockIdx.x;
    const float4* __restrict__ x_row = xh + (size_t)row * nvec8;
    float4* __restrict__ out_row = out + (size_t)row * (nvec8 * 2);

    __shared__ float smax[NUM_WARPS];
    __shared__ float ssum[NUM_WARPS];
    __shared__ float srow_max;
    __shared__ float srow_sum;

    const int tid = threadIdx.x;
    const int lane = tid & 31;
    const int wid = tid >> 5;

    float z[MAX_ITERS][8];

    // Pass 1: z = a * x + b, cache in registers, track row max.
    float m = -INFINITY;
    #pragma unroll
    for (int it = 0; it < MAX_ITERS; ++it) {
        if (it < iters) {
            int idx = tid + it * BLOCK_SIZE;
            float4 raw = x_row[idx];
            const __half2* h = reinterpret_cast<const __half2*>(&raw);
            float4 av0 = a[2 * idx];
            float4 av1 = a[2 * idx + 1];
            float4 bv0 = b[2 * idx];
            float4 bv1 = b[2 * idx + 1];
            float2 f0 = __half22float2(h[0]);
            float2 f1 = __half22float2(h[1]);
            float2 f2 = __half22float2(h[2]);
            float2 f3 = __half22float2(h[3]);
            z[it][0] = fmaf(av0.x, f0.x, bv0.x);
            z[it][1] = fmaf(av0.y, f0.y, bv0.y);
            z[it][2] = fmaf(av0.z, f1.x, bv0.z);
            z[it][3] = fmaf(av0.w, f1.y, bv0.w);
            z[it][4] = fmaf(av1.x, f2.x, bv1.x);
            z[it][5] = fmaf(av1.y, f2.y, bv1.y);
            z[it][6] = fmaf(av1.z, f3.x, bv1.z);
            z[it][7] = fmaf(av1.w, f3.y, bv1.w);
            #pragma unroll
            for (int k = 0; k < 8; ++k) m = fmaxf(m, z[it][k]);
        }
    }
    m = warp_reduce_max(m);
    if (lane == 0) smax[wid] = m;
    __syncthreads();
    if (wid == 0) {
        float v = (lane < NUM_WARPS) ? smax[lane] : -INFINITY;
        v = warp_reduce_max(v);
        if (lane == 0) srow_max = v;
    }
    __syncthreads();
    const float row_max = srow_max;

    // Pass 2: exponentiate (from registers) and accumulate partition sum.
    float s = 0.0f;
    #pragma unroll
    for (int it = 0; it < MAX_ITERS; ++it) {
        if (it < iters) {
            #pragma unroll
            for (int k = 0; k < 8; ++k) {
                z[it][k] = expf(z[it][k] - row_max);
                s += z[it][k];
            }
        }
    }
    s = warp_reduce_sum(s);
    if (lane == 0) ssum[wid] = s;
    __syncthreads();
    if (wid == 0) {
        float v = (lane < NUM_WARPS) ? ssum[lane] : 0.0f;
        v = warp_reduce_sum(v);
        if (lane == 0) srow_sum = v;
    }
    __syncthreads();
    const float inv_sum = 1.0f / srow_sum;

    // Pass 3: normalize and store as fp32.
    #pragma unroll
    for (int it = 0; it < MAX_ITERS; ++it) {
        if (it < iters) {
            int idx = tid + it * BLOCK_SIZE;
            float4 o0, o1;
            o0.x = z[it][0] * inv_sum;
            o0.y = z[it][1] * inv_sum;
            o0.z = z[it][2] * inv_sum;
            o0.w = z[it][3] * inv_sum;
            o1.x = z[it][4] * inv_sum;
            o1.y = z[it][5] * inv_sum;
            o1.z = z[it][6] * inv_sum;
            o1.w = z[it][7] * inv_sum;
            out_row[2 * idx] = o0;
            out_row[2 * idx + 1] = o1;
        }
    }
}

torch::Tensor fused_bn_scale_softmax_half(
    torch::Tensor xh,
    torch::Tensor gamma,
    torch::Tensor beta,
    torch::Tensor scale,
    torch::Tensor running_mean,
    torch::Tensor running_var,
    torch::Tensor nbt,
    double momentum,
    double eps,
    bool training)
{
    TORCH_CHECK(xh.is_cuda(), "x must be a CUDA tensor");
    TORCH_CHECK(xh.scalar_type() == at::kHalf, "x must be float16");
    TORCH_CHECK(xh.dim() == 2, "x must be 2D");
    TORCH_CHECK(xh.is_contiguous() && gamma.is_contiguous() && beta.is_contiguous() &&
                scale.is_contiguous() && running_mean.is_contiguous() &&
                running_var.is_contiguous(), "tensors must be contiguous");

    const int batch = xh.size(0);
    const int n = xh.size(1);
    TORCH_CHECK(n % (8 * BLOCK_SIZE) == 0, "feature dim must be divisible by 2048");
    const int nvec8 = n / 8;
    const int iters = nvec8 / BLOCK_SIZE;
    TORCH_CHECK(iters >= 1 && iters <= MAX_ITERS, "unsupported feature dim");

    auto float_opts = gamma.options().dtype(at::kFloat);
    auto a = torch::empty({n}, float_opts);
    auto b = torch::empty({n}, float_opts);
    auto out = torch::empty({batch, n}, float_opts);

    cudaStream_t stream = at::cuda::getCurrentCUDAStream();

    torch::Tensor stats;
    const double* sum_ptr = nullptr;
    const double* sumsq_ptr = nullptr;
    if (training) {
        stats = torch::empty({2 * n}, float_opts.dtype(at::kDouble));
        double* sp = stats.data_ptr<double>();
        cudaMemsetAsync(sp, 0, sizeof(double) * 2 * n, stream);
        dim3 stats_grid(nvec8 / STATS_THREADS, (batch + ROWS_PER_BLOCK - 1) / ROWS_PER_BLOCK);
        col_stats_half_kernel<<<stats_grid, STATS_THREADS, 0, stream>>>(
            reinterpret_cast<const float4*>(xh.data_ptr<at::Half>()),
            sp,
            sp + n,
            batch,
            nvec8,
            ROWS_PER_BLOCK);
        sum_ptr = sp;
        sumsq_ptr = sp + n;
    }

    const int coef_blocks = (n + BLOCK_SIZE - 1) / BLOCK_SIZE;
    finish_coef_kernel<<<coef_blocks, BLOCK_SIZE, 0, stream>>>(
        sum_ptr,
        sumsq_ptr,
        running_mean.data_ptr<float>(),
        running_var.data_ptr<float>(),
        reinterpret_cast<long long*>(nbt.data_ptr<int64_t>()),
        gamma.data_ptr<float>(),
        beta.data_ptr<float>(),
        scale.data_ptr<float>(),
        a.data_ptr<float>(),
        b.data_ptr<float>(),
        momentum,
        eps,
        n,
        batch,
        training ? 1 : 0);

    fused_affine_softmax_half_kernel<<<batch, BLOCK_SIZE, 0, stream>>>(
        reinterpret_cast<const float4*>(xh.data_ptr<at::Half>()),
        reinterpret_cast<const float4*>(a.data_ptr<float>()),
        reinterpret_cast<const float4*>(b.data_ptr<float>()),
        reinterpret_cast<float4*>(out.data_ptr<float>()),
        nvec8,
        iters);

    return out;
}
"""

_cpp_source = (
    "torch::Tensor fused_bn_scale_softmax_half(torch::Tensor xh, "
    "torch::Tensor gamma, torch::Tensor beta, torch::Tensor scale, "
    "torch::Tensor running_mean, torch::Tensor running_var, torch::Tensor nbt, "
    "double momentum, double eps, bool training);"
)

_fused_ops = load_inline(
    name="fused_half_gemm_bn_scale_softmax_ext_v1",
    cpp_sources=_cpp_source,
    cuda_sources=_cuda_source,
    functions=["fused_bn_scale_softmax_half"],
    extra_cflags=["-O3"],
    extra_cuda_cflags=["-O3"],
    verbose=False,
)

_BLOCK_SIZE = 256
_MAX_ITERS = 4


class ModelNew(nn.Module):
    """
    Optimized version of Model:
      * The Linear layer runs as an fp16 tensor-core GEMM (fp32 accumulation)
        using a cached fp16 copy of the weights.
      * BatchNorm batch statistics use a custom double-precision reduction.
      * BatchNorm + scalar scale + Softmax are fused into a single custom
        CUDA kernel (plus a tiny coefficient kernel), reading the GEMM output
        once and writing the final probabilities once.
    Falls back to the original ops for unsupported configurations.
    """

    def __init__(self, in_features, out_features, bn_eps=1e-5, bn_momentum=0.1, scale_shape=(1,)):
        super(ModelNew, self).__init__()
        self.gemm = nn.Linear(in_features, out_features)
        self.bn = nn.BatchNorm1d(out_features, eps=bn_eps, momentum=bn_momentum)
        self.scale = nn.Parameter(torch.ones(scale_shape))
        self.out_features = out_features
        self._half_cache = None

    def _half_gemm_params(self):
        w = self.gemm.weight
        key = (w._version, w.device)
        cache = self._half_cache
        if cache is None or cache[0] is not w or cache[1] != key:
            wh = w.detach().to(torch.float16).contiguous()
            bias = self.gemm.bias
            bh = bias.detach().to(torch.float16).contiguous() if bias is not None else None
            cache = (w, key, wh, bh)
            self._half_cache = cache
        return cache[2], cache[3]

    def forward(self, x):
        bn = self.bn
        n = self.out_features

        fused_ok = (
            x.is_cuda
            and x.dtype == torch.float32
            and x.dim() == 2
            and bn.affine
            and bn.track_running_stats
            and bn.momentum is not None
            and bn.running_mean is not None
            and self.gemm.bias is not None
            and self.scale.numel() == 1
            and (n % (8 * _BLOCK_SIZE)) == 0
            and 1 <= (n // (8 * _BLOCK_SIZE)) <= _MAX_ITERS
        )

        if fused_ok:
            if not x.is_contiguous():
                x = x.contiguous()
            wh, bh = self._half_gemm_params()
            xh = F.linear(x.half(), wh, bh)
            return _fused_ops.fused_bn_scale_softmax_half(
                xh,
                bn.weight,
                bn.bias,
                self.scale,
                bn.running_mean,
                bn.running_var,
                bn.num_batches_tracked,
                float(bn.momentum),
                float(bn.eps),
                bool(bn.training),
            )

        # Generic fallback: original operator sequence.
        x = self.gemm(x)
        x = bn(x)
        x = self.scale * x
        return F.softmax(x, dim=1)
```
Result of evaluating it:
The solution is correct on the test inputs. Mean runtime 0.762 ms; the PyTorch reference (with TF32 enabled) takes 1.34 ms; speedup 1.759x.
Profiler, top device kernels of one forward pass of your solution:
| device kernel | total device time (us) | calls |
|---|---|---|
| sm80_xmma_gemm_f16f16_f16f32_f32_tn_n_tilesize96x128x32_stage4_warpsize2x2x1_tensor16x8x16 | 583.5 | 1 |
| fused_affine_softmax_half_kernel(float4 const*, float4 const*, float4 const*, float4*, int | 52.0 | 1 |
| void at::native::vectorized_elementwise_kernel<4, at::native::float16_copy_kernel_cuda(at: | 42.6 | 1 |
| col_stats_half_kernel(float4 const*, double*, double*, int, int, int) | 35.7 | 1 |
| finish_coef_kernel(double const*, double const*, float*, float*, long long*, float const*, | 4.2 | 1 |
| Memset (Device) | 2.4 | 1 |

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.
