You write custom CUDA kernels to replace the pytorch operators in the given architecture to get speedups. 

    You have complete freedom to choose the set of operators you want to replace. You may make the decision to replace some operators with custom CUDA kernels and leave others unchanged. You may replace multiple operators with custom implementations, consider operator fusion opportunities (combining multiple operators into a single kernel, for example, combining matmul+relu), or algorithmic changes (such as online softmax). You are only limited by your imagination.


        Here's an example to show you the syntax of inline embedding custom CUDA operators in torch: The example given architecture is: 

        ``` 

        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F


class Model(nn.Module):
    def __init__(self) -> None:
        super().__init__()

    def forward(self, a, b):
        return a + b


def get_inputs():
    # randomly generate input tensors based on the model architecture
    a = torch.randn(1, 128).cuda()
    b = torch.randn(1, 128).cuda()
    return [a, b]


def get_init_inputs():
    # randomly generate tensors required for initialization based on the model architecture
    return []

        ``` 

        The example new arch with custom CUDA kernels looks like this:
        ```
        # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Define the custom CUDA kernel for element-wise addition
elementwise_add_source = """
#include <torch/extension.h>
#include <cuda_runtime.h>

__global__ void elementwise_add_kernel(const float* a, const float* b, float* out, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        out[idx] = a[idx] + b[idx];
    }
}

torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b) {
    auto size = a.numel();
    auto out = torch::zeros_like(a);

    const int block_size = 256;
    const int num_blocks = (size + block_size - 1) / block_size;

    elementwise_add_kernel<<<num_blocks, block_size>>>(a.data_ptr<float>(), b.data_ptr<float>(), out.data_ptr<float>(), size);

    return out;
}
"""

elementwise_add_cpp_source = (
    "torch::Tensor elementwise_add_cuda(torch::Tensor a, torch::Tensor b);"
)

# Compile the inline CUDA code for element-wise addition
elementwise_add = load_inline(
    name="elementwise_add",
    cpp_sources=elementwise_add_cpp_source,
    cuda_sources=elementwise_add_source,
    functions=["elementwise_add_cuda"],
    verbose=True,
    extra_cflags=[""],
    extra_ldflags=[""],
)


class ModelNew(nn.Module):
    def __init__(self) -> None:
        super().__init__()
        self.elementwise_add = elementwise_add

    def forward(self, a, b):
        return self.elementwise_add.elementwise_add_cuda(a, b)

        ``` 

        
    You are given the following architecture: 

    ```
    # Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Model that performs a matrix multiplication, subtraction, multiplication, and ReLU activation.
    """
    def __init__(self, in_features, out_features, subtract_value, multiply_value):
        super(Model, self).__init__()
        self.linear = nn.Linear(in_features, out_features)
        self.subtract_value = subtract_value
        self.multiply_value = multiply_value

    def forward(self, x):
        x = self.linear(x)
        x = x - self.subtract_value
        x = x * self.multiply_value
        x = torch.relu(x)
        return x

batch_size = 1024
in_features = 8192
out_features = 8192
subtract_value = 2.0
multiply_value = 1.5

def get_inputs():
    return [torch.rand(batch_size, in_features)]

def get_init_inputs():
    return [in_features, out_features, subtract_value, multiply_value]
    ```
    
Optimize the architecture named Model with custom CUDA operators! Name your optimized output architecture ModelNew. Output the new code in codeblocks. Please generate real code, NOT pseudocode, make sure the code compiles and is fully functional. Just output the new model code, no other text, and NO testing code! 



This is turn 5 of 6 for this task. Your previous solution (turn 4) was:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Fully fused operator:
#   out = relu( mul * (x @ weight^T + bias - sub) )
#       = relu( mul * (x @ weight^T) + mul * (bias - sub) )
# A tiny kernel builds bias_eff = mul * (bias - sub); a single cublasLt GEMM
# with TF32 tensor-core math (explicitly allowed for this task) and the fused
# RELU_BIAS epilogue computes everything else (alpha = mul).
#
# Compared to the previous version:
#   * One-time plan cache: cublasLt descriptors, the chosen algorithm and the
#     workspace are created once per (M, N, K, device) and reused every call.
#   * Exhaustive one-time autotune: besides the cublasLt heuristics, all
#     enumerated algorithms are validated and timed, for BOTH the TN layout
#     (weight as-is) and the NN layout (pre-transposed weight, cached with
#     version checking). The fastest overall is kept.
#   * bias_eff is cached and only recomputed when the bias tensor actually
#     changes (pointer/version check), into a persistent buffer so the cached
#     epilogue bias pointer stays valid.
#   * No per-call reshapes/views; the output is allocated in its final shape.
_cpp_src = """
torch::Tensor linear_sub_mul_relu(torch::Tensor x, torch::Tensor weight,
                                  torch::Tensor bias, double sub, double mul);
torch::Tensor sub_mul_relu(torch::Tensor y, double sub, double mul);
"""

_cuda_src = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <cublasLt.h>
#include <cuda_runtime.h>
#include <cstdint>
#include <cstring>
#include <map>
#include <tuple>
#include <vector>

#define CUBLASLT_CHECK(expr)                                                   \
  do {                                                                         \
    cublasStatus_t _status = (expr);                                           \
    TORCH_CHECK(_status == CUBLAS_STATUS_SUCCESS, "cublasLt call failed: ",    \
                #expr, " status=", (int)_status);                              \
  } while (0)

namespace {

cublasLtHandle_t getLtHandle() {
  static cublasLtHandle_t handle = nullptr;
  if (handle == nullptr) {
    CUBLASLT_CHECK(cublasLtCreate(&handle));
  }
  return handle;
}

// TF32 tensor-core math is explicitly allowed for this task (sm_80+).
bool tf32Supported() {
  static int supported = -1;
  if (supported < 0) {
    int dev = 0;
    supported = 0;
    if (cudaGetDevice(&dev) == cudaSuccess) {
      int major = 0;
      if (cudaDeviceGetAttribute(&major, cudaDevAttrComputeCapabilityMajor,
                                 dev) == cudaSuccess &&
          major >= 8) {
        supported = 1;
      }
    }
  }
  return supported == 1;
}

inline int64_t ver_of(const at::Tensor& t) {
  return (int64_t)t.unsafeGetTensorImpl()->version_counter().current_version();
}

__global__ void bias_transform_kernel(const float* __restrict__ bias,
                                      float* __restrict__ out, int n,
                                      float sub, float mul) {
  int i = blockIdx.x * blockDim.x + threadIdx.x;
  if (i < n) {
    out[i] = (bias[i] - sub) * mul;
  }
}

__global__ void sub_mul_relu_vec4_kernel(const float4* __restrict__ in,
                                         float4* __restrict__ out, long n4,
                                         float sub, float mul) {
  const long stride = (long)gridDim.x * blockDim.x;
  for (long i = (long)blockIdx.x * blockDim.x + threadIdx.x; i < n4;
       i += stride) {
    float4 v = in[i];
    v.x = fmaxf((v.x - sub) * mul, 0.0f);
    v.y = fmaxf((v.y - sub) * mul, 0.0f);
    v.z = fmaxf((v.z - sub) * mul, 0.0f);
    v.w = fmaxf((v.w - sub) * mul, 0.0f);
    out[i] = v;
  }
}

__global__ void sub_mul_relu_kernel(const float* __restrict__ in,
                                    float* __restrict__ out, long n, float sub,
                                    float mul) {
  const long stride = (long)gridDim.x * blockDim.x;
  for (long i = (long)blockIdx.x * blockDim.x + threadIdx.x; i < n;
       i += stride) {
    out[i] = fmaxf((in[i] - sub) * mul, 0.0f);
  }
}

struct GemmPlan {
  cublasLtMatmulDesc_t op_desc = nullptr;
  cublasLtMatrixLayout_t a_desc = nullptr;
  cublasLtMatrixLayout_t b_desc = nullptr;
  cublasLtMatrixLayout_t c_desc = nullptr;
  cublasLtMatmulHeuristicResult_t heuristic{};
  bool use_wt = false;
  at::Tensor workspace;
  at::Tensor bias_eff;
  at::Tensor weight_t;
  at::Tensor bias_src;
  at::Tensor weight_src;
  const void* bias_src_ptr = nullptr;
  const void* weight_src_ptr = nullptr;
  int64_t bias_src_version = -1;
  int64_t weight_src_version = -1;
  double sub = 0.0;
  double mul = 0.0;
};

cublasLtMatmulDesc_t make_op_desc(cublasComputeType_t ct,
                                  cublasOperation_t transa, float* bias_ptr) {
  cublasLtMatmulDesc_t d = nullptr;
  CUBLASLT_CHECK(cublasLtMatmulDescCreate(&d, ct, CUDA_R_32F));
  cublasOperation_t tb = CUBLAS_OP_N;
  CUBLASLT_CHECK(cublasLtMatmulDescSetAttribute(
      d, CUBLASLT_MATMUL_DESC_TRANSA, &transa, sizeof(transa)));
  CUBLASLT_CHECK(cublasLtMatmulDescSetAttribute(d, CUBLASLT_MATMUL_DESC_TRANSB,
                                                &tb, sizeof(tb)));
  cublasLtEpilogue_t epi = CUBLASLT_EPILOGUE_RELU_BIAS;
  CUBLASLT_CHECK(cublasLtMatmulDescSetAttribute(
      d, CUBLASLT_MATMUL_DESC_EPILOGUE, &epi, sizeof(epi)));
  CUBLASLT_CHECK(cublasLtMatmulDescSetAttribute(
      d, CUBLASLT_MATMUL_DESC_BIAS_POINTER, &bias_ptr, sizeof(bias_ptr)));
  return d;
}

struct TimedAlgo {
  cublasLtMatmulHeuristicResult_t hr;
  float ms;
};

// Gather candidate algorithms (cublasLt heuristics + full enumeration) for one
// matrix-layout configuration and micro-benchmark each of them.
void collect_and_time(std::vector<TimedAlgo>& sink, cublasComputeType_t ct,
                      cublasLtMatmulDesc_t op_desc,
                      cublasLtMatrixLayout_t a_desc,
                      cublasLtMatrixLayout_t b_desc,
                      cublasLtMatrixLayout_t c_desc, const float* A,
                      const float* B, float* C, float alpha, float beta,
                      void* ws_ptr, size_t ws_cap, int max_heur, int max_enum,
                      cudaStream_t stream) {
  cublasLtHandle_t handle = getLtHandle();
  std::vector<cublasLtMatmulHeuristicResult_t> cands;

  {
    cublasLtMatmulPreference_t pref = nullptr;
    if (cublasLtMatmulPreferenceCreate(&pref) == CUBLAS_STATUS_SUCCESS) {
      cublasLtMatmulPreferenceSetAttribute(
          pref, CUBLASLT_MATMUL_PREF_MAX_WORKSPACE_BYTES, &ws_cap,
          sizeof(ws_cap));
      std::vector<cublasLtMatmulHeuristicResult_t> hres((size_t)max_heur);
      int nret = 0;
      if (cublasLtMatmulAlgoGetHeuristic(handle, op_desc, a_desc, b_desc,
                                         c_desc, c_desc, pref, max_heur,
                                         hres.data(),
                                         &nret) == CUBLAS_STATUS_SUCCESS) {
        for (int i = 0; i < nret; ++i) {
          if (hres[i].state == CUBLAS_STATUS_SUCCESS &&
              hres[i].workspaceSize <= ws_cap) {
            cands.push_back(hres[i]);
          }
        }
      }
      cublasLtMatmulPreferenceDestroy(pref);
    }
  }

  {
    int ids[64];
    int nids = 0;
    if (cublasLtMatmulAlgoGetIds(handle, ct, CUDA_R_32F, CUDA_R_32F,
                                 CUDA_R_32F, CUDA_R_32F, 64, ids,
                                 &nids) == CUBLAS_STATUS_SUCCESS) {
      int lim = nids < max_enum ? nids : max_enum;
      for (int i = 0; i < lim; ++i) {
        cublasLtMatmulAlgo_t algo;
        std::memset(&algo, 0, sizeof(algo));
        if (cublasLtMatmulAlgoInit(handle, ct, CUDA_R_32F, CUDA_R_32F,
                                   CUDA_R_32F, CUDA_R_32F, ids[i],
                                   &algo) != CUBLAS_STATUS_SUCCESS) {
          continue;
        }
        bool dup = false;
        for (size_t j = 0; j < cands.size(); ++j) {
          if (std::memcmp(&cands[j].algo, &algo, sizeof(algo)) == 0) {
            dup = true;
            break;
          }
        }
        if (dup) continue;
        cublasLtMatmulHeuristicResult_t chk;
        std::memset(&chk, 0, sizeof(chk));
        if (cublasLtMatmulAlgoCheck(handle, op_desc, a_desc, b_desc, c_desc,
                                    c_desc, &algo,
                                    &chk) != CUBLAS_STATUS_SUCCESS) {
          continue;
        }
        if (chk.state != CUBLAS_STATUS_SUCCESS || chk.workspaceSize > ws_cap) {
          continue;
        }
        chk.algo = algo;
        cands.push_back(chk);
      }
    }
  }

  if (cands.empty()) return;

  cudaEvent_t e0, e1;
  cudaEventCreate(&e0);
  cudaEventCreate(&e1);
  for (size_t i = 0; i < cands.size(); ++i) {
    cublasLtMatmulHeuristicResult_t& hr = cands[i];
    cublasStatus_t st =
        cublasLtMatmul(handle, op_desc, &alpha, A, a_desc, B, b_desc, &beta, C,
                       c_desc, C, c_desc, &hr.algo, ws_ptr, hr.workspaceSize,
                       stream);
    if (st != CUBLAS_STATUS_SUCCESS) continue;
    if (cudaStreamSynchronize(stream) != cudaSuccess) continue;
    cudaEventRecord(e0, stream);
    for (int r = 0; r < 3; ++r) {
      cublasLtMatmul(handle, op_desc, &alpha, A, a_desc, B, b_desc, &beta, C,
                     c_desc, C, c_desc, &hr.algo, ws_ptr, hr.workspaceSize,
                     stream);
    }
    cudaEventRecord(e1, stream);
    cudaEventSynchronize(e1);
    float ms = 0.0f;
    cudaEventElapsedTime(&ms, e0, e1);
    TimedAlgo ta;
    ta.hr = hr;
    ta.ms = ms / 3.0f;
    sink.push_back(ta);
  }
  cudaEventDestroy(e0);
  cudaEventDestroy(e1);
}

const TimedAlgo* best_of(const std::vector<TimedAlgo>& v) {
  const TimedAlgo* b = nullptr;
  for (size_t i = 0; i < v.size(); ++i) {
    if (b == nullptr || v[i].ms < b->ms) b = &v[i];
  }
  return b;
}

// Build a plan for a fixed (M, N, K): autotune both the TN layout (weight
// as-is) and the NN layout (pre-transposed weight) and keep the fastest.
GemmPlan create_plan(int64_t M, int64_t N, int64_t K, int use_tf32,
                     const float* x_ptr, const at::Tensor& w, float* out_ptr,
                     float* bias_eff_ptr, float alpha, cudaStream_t stream) {
  const cublasComputeType_t ct =
      use_tf32 ? CUBLAS_COMPUTE_32F_FAST_TF32 : CUBLAS_COMPUTE_32F;
  const float beta = 0.0f;
  const size_t ws_cap = (size_t)256 << 20;
  auto scratch = at::empty({(int64_t)ws_cap}, w.options().dtype(at::kByte));
  void* ws_ptr = scratch.data_ptr();

  // Row-major C(M,N) = X(M,K) * W^T(K,N) as the equivalent column-major
  // problem C^T(N,M) = W(N,K) * X^T(K,M).
  cublasLtMatrixLayout_t b_desc = nullptr, c_desc = nullptr;
  CUBLASLT_CHECK(cublasLtMatrixLayoutCreate(&b_desc, CUDA_R_32F, K, M, K));
  CUBLASLT_CHECK(cublasLtMatrixLayoutCreate(&c_desc, CUDA_R_32F, N, M, N));

  // Config 1 (TN): A = weight buffer viewed col-major (K,N), op(A) = A^T.
  cublasLtMatmulDesc_t op_tn = make_op_desc(ct, CUBLAS_OP_T, bias_eff_ptr);
  cublasLtMatrixLayout_t a_tn = nullptr;
  CUBLASLT_CHECK(cublasLtMatrixLayoutCreate(&a_tn, CUDA_R_32F, K, N, K));
  std::vector<TimedAlgo> res_tn;
  collect_and_time(res_tn, ct, op_tn, a_tn, b_desc, c_desc,
                   w.data_ptr<float>(), x_ptr, out_ptr, alpha, beta, ws_ptr,
                   ws_cap, 16, 24, stream);

  // Config 2 (NN): A = pre-transposed weight viewed col-major (N,K), op(A)=A.
  at::Tensor wt = w.t().contiguous();
  cublasLtMatmulDesc_t op_nn = make_op_desc(ct, CUBLAS_OP_N, bias_eff_ptr);
  cublasLtMatrixLayout_t a_nn = nullptr;
  CUBLASLT_CHECK(cublasLtMatrixLayoutCreate(&a_nn, CUDA_R_32F, N, K, N));
  std::vector<TimedAlgo> res_nn;
  collect_and_time(res_nn, ct, op_nn, a_nn, b_desc, c_desc,
                   wt.data_ptr<float>(), x_ptr, out_ptr, alpha, beta, ws_ptr,
                   ws_cap, 16, 24, stream);

  const TimedAlgo* bt = best_of(res_tn);
  const TimedAlgo* bn = best_of(res_nn);
  TORCH_CHECK(bt != nullptr || bn != nullptr,
              "cublasLt found no runnable algorithm");
  const bool choose_nn = (bn != nullptr) && (bt == nullptr || bn->ms < bt->ms);

  GemmPlan plan;
  plan.use_wt = choose_nn;
  if (choose_nn) {
    plan.op_desc = op_nn;
    plan.a_desc = a_nn;
    plan.heuristic = bn->hr;
    plan.weight_t = wt;
    cublasLtMatmulDescDestroy(op_tn);
    cublasLtMatrixLayoutDestroy(a_tn);
  } else {
    plan.op_desc = op_tn;
    plan.a_desc = a_tn;
    plan.heuristic = bt->hr;
    cublasLtMatmulDescDestroy(op_nn);
    cublasLtMatrixLayoutDestroy(a_nn);
  }
  plan.b_desc = b_desc;
  plan.c_desc = c_desc;
  const size_t ws_need =
      plan.heuristic.workspaceSize > 0 ? plan.heuristic.workspaceSize : 1;
  plan.workspace =
      at::empty({(int64_t)ws_need}, w.options().dtype(at::kByte));
  return plan;
}

}  // namespace

torch::Tensor linear_sub_mul_relu(torch::Tensor x, torch::Tensor weight,
                                  torch::Tensor bias, double sub, double mul) {
  TORCH_CHECK(x.is_cuda() && weight.is_cuda() && bias.is_cuda(),
              "CUDA tensors required");
  TORCH_CHECK(x.scalar_type() == at::kFloat &&
                  weight.scalar_type() == at::kFloat &&
                  bias.scalar_type() == at::kFloat,
              "FP32 tensors required");
  TORCH_CHECK(x.dim() >= 2, "x must have at least 2 dims");
  TORCH_CHECK(weight.dim() == 2, "weight must be 2D");

  const c10::cuda::OptionalCUDAGuard guard(at::device_of(x));

  auto xc = x.contiguous();
  auto wc = weight.contiguous();
  auto bc = bias.contiguous();

  const int64_t K = xc.size(-1);
  const int64_t N = wc.size(0);
  TORCH_CHECK(wc.size(1) == K, "weight shape mismatch");
  TORCH_CHECK(bc.numel() == N, "bias shape mismatch");
  TORCH_CHECK(K > 0, "in_features must be positive");
  TORCH_CHECK(K <= INT32_MAX && N <= INT32_MAX, "unsupported dims");
  const int64_t M = xc.numel() / K;
  TORCH_CHECK(M <= INT32_MAX, "unsupported dims");

  auto out_sizes = xc.sizes().vec();
  out_sizes.back() = N;
  auto out = at::empty(out_sizes, xc.options());
  if (M == 0 || N == 0) {
    return out;
  }

  // The cached algorithm assumes 16-byte aligned pointers (always true for
  // freshly allocated CUDA tensors; fix up exotic views just in case).
  if ((reinterpret_cast<uintptr_t>(xc.data_ptr()) & 15) != 0) xc = xc.clone();
  if ((reinterpret_cast<uintptr_t>(wc.data_ptr()) & 15) != 0) wc = wc.clone();

  cudaStream_t stream = at::cuda::getCurrentCUDAStream();
  const int use_tf32 = tf32Supported() ? 1 : 0;
  const int dev = (int)xc.get_device();
  const float alpha = (float)mul;
  const float beta = 0.0f;

  typedef std::tuple<int64_t, int64_t, int64_t, int, int> Key;
  static std::map<Key, GemmPlan>* plans = new std::map<Key, GemmPlan>();
  const Key key = std::make_tuple(M, N, K, use_tf32, dev);

  std::map<Key, GemmPlan>::iterator it = plans->find(key);
  if (it == plans->end()) {
    auto bias_eff = at::empty({N}, xc.options());
    {
      const int threads = 256;
      const int blocks = (int)((N + threads - 1) / threads);
      bias_transform_kernel<<<blocks, threads, 0, stream>>>(
          bc.data_ptr<float>(), bias_eff.data_ptr<float>(), (int)N, (float)sub,
          (float)mul);
    }
    GemmPlan p = create_plan(M, N, K, use_tf32, xc.data_ptr<float>(), wc,
                             out.data_ptr<float>(),
                             bias_eff.data_ptr<float>(), alpha, stream);
    p.bias_eff = bias_eff;
    p.bias_src = bc;  // keep the storage alive so its pointer cannot be reused
    p.bias_src_ptr = bc.data_ptr();
    p.bias_src_version = ver_of(bc);
    p.sub = sub;
    p.mul = mul;
    if (p.use_wt) {
      p.weight_src = wc;
      p.weight_src_ptr = wc.data_ptr();
      p.weight_src_version = ver_of(wc);
    }
    it = plans->emplace(key, std::move(p)).first;
  }
  GemmPlan& plan = it->second;

  // Refresh bias_eff only if the bias (or scalars) actually changed.
  const bool bias_ok = plan.bias_src_ptr == bc.data_ptr() &&
                       plan.bias_src_version == ver_of(bc) &&
                       plan.sub == sub && plan.mul == mul;
  if (!bias_ok) {
    const int threads = 256;
    const int blocks = (int)((N + threads - 1) / threads);
    bias_transform_kernel<<<blocks, threads, 0, stream>>>(
        bc.data_ptr<float>(), plan.bias_eff.data_ptr<float>(), (int)N,
        (float)sub, (float)mul);
    plan.bias_src = bc;
    plan.bias_src_ptr = bc.data_ptr();
    plan.bias_src_version = ver_of(bc);
    plan.sub = sub;
    plan.mul = mul;
  }

  if (plan.use_wt) {
    const bool w_ok = plan.weight_src_ptr == wc.data_ptr() &&
                      plan.weight_src_version == ver_of(wc);
    if (!w_ok) {
      plan.weight_t.copy_(wc.t());
      plan.weight_src = wc;
      plan.weight_src_ptr = wc.data_ptr();
      plan.weight_src_version = ver_of(wc);
    }
  }

  const float* A = plan.use_wt ? plan.weight_t.data_ptr<float>()
                               : wc.data_ptr<float>();
  CUBLASLT_CHECK(cublasLtMatmul(
      getLtHandle(), plan.op_desc, &alpha, A, plan.a_desc,
      xc.data_ptr<float>(), plan.b_desc, &beta, out.data_ptr<float>(),
      plan.c_desc, out.data_ptr<float>(), plan.c_desc, &plan.heuristic.algo,
      plan.workspace.data_ptr(), plan.heuristic.workspaceSize, stream));

  return out;
}

torch::Tensor sub_mul_relu(torch::Tensor y, double sub, double mul) {
  TORCH_CHECK(y.is_cuda(), "CUDA tensor required");
  TORCH_CHECK(y.scalar_type() == at::kFloat, "FP32 tensor required");
  auto yc = y.contiguous();
  auto out = at::empty_like(yc);
  const long n = (long)yc.numel();
  if (n == 0) {
    return out;
  }
  cudaStream_t stream = at::cuda::getCurrentCUDAStream();
  const float* in_ptr = yc.data_ptr<float>();
  float* out_ptr = out.data_ptr<float>();
  const int threads = 256;
  if ((n & 3) == 0) {
    const long n4 = n >> 2;
    long blocks = (n4 + threads - 1) / threads;
    if (blocks > 16384) blocks = 16384;
    sub_mul_relu_vec4_kernel<<<(int)blocks, threads, 0, stream>>>(
        reinterpret_cast<const float4*>(in_ptr),
        reinterpret_cast<float4*>(out_ptr), n4, (float)sub, (float)mul);
  } else {
    long blocks = (n + threads - 1) / threads;
    if (blocks > 65536) blocks = 65536;
    sub_mul_relu_kernel<<<(int)blocks, threads, 0, stream>>>(
        in_ptr, out_ptr, n, (float)sub, (float)mul);
  }
  return out;
}
"""

_ext = load_inline(
    name="fused_linear_sub_mul_relu_v4",
    cpp_sources=_cpp_src,
    cuda_sources=_cuda_src,
    functions=["linear_sub_mul_relu", "sub_mul_relu"],
    verbose=False,
    extra_cflags=["-O3"],
    extra_cuda_cflags=["-O3"],
    extra_ldflags=["-lcublas", "-lcublasLt"],
)

_fused = _ext.linear_sub_mul_relu
_ew = _ext.sub_mul_relu


class ModelNew(nn.Module):
    """
    Optimized version of Model.

    The whole forward (matmul + bias + subtract + multiply + ReLU) is fused
    into a single custom cublasLt-based CUDA operator by folding the subtract
    into the bias vector and the multiply into the GEMM alpha, using a TF32
    tensor-core GEMM (explicitly allowed) with a fused ReLU+bias epilogue.
    Descriptors, the autotuned algorithm (searched exhaustively over both the
    TN and pre-transposed NN layouts), the workspace and the transformed bias
    are all cached across calls. If the fused path is unavailable, it falls
    back to cuBLAS linear followed by a custom fused subtract-multiply-ReLU
    kernel.
    """

    def __init__(self, in_features, out_features, subtract_value,
                 multiply_value):
        super(ModelNew, self).__init__()
        self.linear = nn.Linear(in_features, out_features)
        self.subtract_value = float(subtract_value)
        self.multiply_value = float(multiply_value)
        self._use_fused = True
        # TF32 tensor-core math is explicitly permitted for this task; make
        # sure the ATen fallback path also benefits from it.
        if torch.cuda.is_available():
            try:
                torch.backends.cuda.matmul.allow_tf32 = True
            except Exception:
                pass

    def forward(self, x):
        if x.is_cuda and x.dtype == torch.float32:
            lin = self.linear
            if self._use_fused and lin.bias is not None:
                try:
                    return _fused(x, lin.weight, lin.bias,
                                  self.subtract_value, self.multiply_value)
                except RuntimeError:
                    self._use_fused = False
            return _ew(F.linear(x, lin.weight, lin.bias),
                       self.subtract_value, self.multiply_value)
        # CPU fallback: reference computation.
        x = self.linear(x)
        x = x - self.subtract_value
        x = x * self.multiply_value
        return torch.relu(x)
```
Result of evaluating it:
The solution failed to compile. Error output:
```
RuntimeError: Error building extension 'fused_linear_sub_mul_relu_v4': [1/3] /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/bin/nvcc -MD -MF cuda.cuda.o.d -DTORCH_EXTENSION_NAME=fused_linear_sub_mul_relu_v4 -DTORCH_API_INCLUDE_EXTENSION_H -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include/torch/csrc/api/include -isystem /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/include -isystem /usr/include/python3.12 -D__CUDA_NO_HALF_OPERATORS__ -D__CUDA_NO_HALF_CONVERSIONS__ -D__CUDA_NO_BFLOAT16_CONVERSIONS__ -D__CUDA_NO_HALF2_OPERATORS__ --expt-relaxed-constexpr -gencode=arch=compute_80,code=sm_80 --compiler-options '-fPIC' -O3 -std=c++20 -c /srv/jobs/1791684524125406578-526805-0/build/fused_linear_sub_mul_relu_v4/cuda.cu -o cuda.cuda.o 
FAILED: [code=134] cuda.cuda.o 
/opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/bin/nvcc -MD -MF cuda.cuda.o.d -DTORCH_EXTENSION_NAME=fused_linear_sub_mul_relu_v4 -DTORCH_API_INCLUDE_EXTENSION_H -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include/torch/csrc/api/include -isystem /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/include -isystem /usr/include/python3.12 -D__CUDA_NO_HALF_OPERATORS__ -D__CUDA_NO_HALF_CONVERSIONS__ -D__CUDA_NO_BFLOAT16_CONVERSIONS__ -D__CUDA_NO_HALF2_OPERATORS__ --expt-relaxed-constexpr -gencode=arch=compute_80,code=sm_80 --compiler-options '-fPIC' -O3 -std=c++20 -c /srv/jobs/1791684524125406578-526805-0/build/fused_linear_sub_mul_relu_v4/cuda.cu -o cuda.cuda.o 
/usr/include/c++/13/bits/stl_construct.h(88): internal error: assertion failed at: "lexical.c", line 22316 in find_allocated_name_reference

   __location->~_Tp();
   ^

1 catastrophic error detected in the compilation of "/srv/jobs/1791684524125406578-526805-0/build/fused_linear_sub_mul_relu_v4/cuda.cu".
Compilation aborted.
Aborted
[2/3] c++ -MMD -MF main.o.d -DTORCH_EXTENSION_NAME=fused_linear_sub_mul_relu_v4 -DTORCH_API_INCLUDE_EXTENSION_H -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include -isystem /opt/kbv/v/lib/python3.12/site-packages/torch/include/torch/csrc/api/include -isystem /opt/kbv/v/lib/python3.12/site-packages/nvidia/cu13/include -isystem /usr/include/python3.12 -fPIC -std=c++20 -O3 -c /srv/jobs/1791684524125406578-526805-0/build/fused_linear_sub_mul_relu_v4/main.cpp -o main.o 
ninja: build stopped: subcommand failed.

```

The fastest correct solution so far (1.144x speedup) is:
```python
# Copyright (c) Meta Platforms, Inc. and affiliates.
# All rights reserved.
#
# This source code is licensed under the license found in the
# LICENSE file in the root directory of this source tree.

import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

# Fully fused operator:
#   out = relu( mul * (x @ weight^T + bias - sub) )
#       = relu( mul * (x @ weight^T) + mul * (bias - sub) )
# A tiny kernel builds bias_eff = mul * (bias - sub); a single cublasLt GEMM
# with TF32 tensor-core math (explicitly allowed for this task) and the fused
# RELU_BIAS epilogue computes everything else (alpha = mul). On the first
# call for a given (M, N, K) the top cublasLt heuristics are micro-benchmarked
# and the fastest algorithm is cached.
_cpp_src = """
torch::Tensor linear_sub_mul_relu(torch::Tensor x, torch::Tensor weight,
                                  torch::Tensor bias, double sub, double mul);
torch::Tensor sub_mul_relu(torch::Tensor y, double sub, double mul);
"""

_cuda_src = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <cublasLt.h>
#include <cuda_runtime.h>
#include <map>
#include <tuple>

#define CUBLASLT_CHECK(expr)                                                   \
  do {                                                                         \
    cublasStatus_t _status = (expr);                                           \
    TORCH_CHECK(_status == CUBLAS_STATUS_SUCCESS, "cublasLt call failed: ",    \
                #expr, " status=", (int)_status);                              \
  } while (0)

namespace {

cublasLtHandle_t getLtHandle() {
  static cublasLtHandle_t handle = nullptr;
  if (handle == nullptr) {
    CUBLASLT_CHECK(cublasLtCreate(&handle));
  }
  return handle;
}

// TF32 tensor-core math is explicitly allowed for this task (sm_80+).
bool tf32Supported() {
  static int supported = -1;
  if (supported < 0) {
    int dev = 0;
    supported = 0;
    if (cudaGetDevice(&dev) == cudaSuccess) {
      int major = 0;
      if (cudaDeviceGetAttribute(&major, cudaDevAttrComputeCapabilityMajor,
                                 dev) == cudaSuccess &&
          major >= 8) {
        supported = 1;
      }
    }
  }
  return supported == 1;
}

__global__ void bias_transform_kernel(const float* __restrict__ bias,
                                      float* __restrict__ out, int n,
                                      float sub, float mul) {
  int i = blockIdx.x * blockDim.x + threadIdx.x;
  if (i < n) {
    out[i] = (bias[i] - sub) * mul;
  }
}

__global__ void sub_mul_relu_vec4_kernel(const float4* __restrict__ in,
                                         float4* __restrict__ out, long n4,
                                         float sub, float mul) {
  const long stride = (long)gridDim.x * blockDim.x;
  for (long i = (long)blockIdx.x * blockDim.x + threadIdx.x; i < n4;
       i += stride) {
    float4 v = in[i];
    v.x = fmaxf((v.x - sub) * mul, 0.0f);
    v.y = fmaxf((v.y - sub) * mul, 0.0f);
    v.z = fmaxf((v.z - sub) * mul, 0.0f);
    v.w = fmaxf((v.w - sub) * mul, 0.0f);
    out[i] = v;
  }
}

__global__ void sub_mul_relu_kernel(const float* __restrict__ in,
                                    float* __restrict__ out, long n, float sub,
                                    float mul) {
  const long stride = (long)gridDim.x * blockDim.x;
  for (long i = (long)blockIdx.x * blockDim.x + threadIdx.x; i < n;
       i += stride) {
    out[i] = fmaxf((in[i] - sub) * mul, 0.0f);
  }
}

}  // namespace

torch::Tensor linear_sub_mul_relu(torch::Tensor x, torch::Tensor weight,
                                  torch::Tensor bias, double sub, double mul) {
  TORCH_CHECK(x.is_cuda() && weight.is_cuda() && bias.is_cuda(),
              "CUDA tensors required");
  TORCH_CHECK(x.scalar_type() == at::kFloat &&
                  weight.scalar_type() == at::kFloat &&
                  bias.scalar_type() == at::kFloat,
              "FP32 tensors required");
  TORCH_CHECK(x.dim() >= 2, "x must have at least 2 dims");
  TORCH_CHECK(weight.dim() == 2, "weight must be 2D");

  auto xc = x.contiguous();
  auto wc = weight.contiguous();
  auto bc = bias.contiguous();

  const int64_t K = xc.size(-1);
  const int64_t N = wc.size(0);
  TORCH_CHECK(wc.size(1) == K, "weight shape mismatch");
  TORCH_CHECK(bc.numel() == N, "bias shape mismatch");

  auto x2 = xc.reshape({-1, K});
  const int64_t M = x2.size(0);

  auto out_sizes = xc.sizes().vec();
  out_sizes.back() = N;
  auto out = at::empty({M, N}, xc.options());
  if (M == 0 || N == 0) {
    return out.reshape(out_sizes);
  }
  TORCH_CHECK(K > 0 && K <= INT32_MAX && M <= INT32_MAX && N <= INT32_MAX,
              "unsupported dims");

  cudaStream_t stream = at::cuda::getCurrentCUDAStream();

  // bias_eff = (bias - sub) * mul   (one entry per output feature)
  auto bias_eff = at::empty({N}, xc.options());
  {
    const int threads = 256;
    const int blocks = (int)((N + threads - 1) / threads);
    bias_transform_kernel<<<blocks, threads, 0, stream>>>(
        bc.data_ptr<float>(), bias_eff.data_ptr<float>(), (int)N, (float)sub,
        (float)mul);
  }

  const int use_tf32 = tf32Supported() ? 1 : 0;
  const cublasComputeType_t compute_type =
      use_tf32 ? CUBLAS_COMPUTE_32F_FAST_TF32 : CUBLAS_COMPUTE_32F;

  cublasLtMatmulDesc_t op_desc = nullptr;
  CUBLASLT_CHECK(cublasLtMatmulDescCreate(&op_desc, compute_type, CUDA_R_32F));

  // Row-major C(M,N) = X(M,K) * W^T(K,N) is computed as the equivalent
  // column-major problem C^T(N,M) = W(N,K) * X^T(K,M):
  //   A = weight buffer viewed as col-major (K,N), op(A) = A^T = W (N,K)
  //   B = x buffer      viewed as col-major (K,M), op(B) = X^T (K,M)
  cublasOperation_t transa = CUBLAS_OP_T;
  cublasOperation_t transb = CUBLAS_OP_N;
  CUBLASLT_CHECK(cublasLtMatmulDescSetAttribute(
      op_desc, CUBLASLT_MATMUL_DESC_TRANSA, &transa, sizeof(transa)));
  CUBLASLT_CHECK(cublasLtMatmulDescSetAttribute(
      op_desc, CUBLASLT_MATMUL_DESC_TRANSB, &transb, sizeof(transb)));

  cublasLtEpilogue_t epilogue = CUBLASLT_EPILOGUE_RELU_BIAS;
  CUBLASLT_CHECK(cublasLtMatmulDescSetAttribute(
      op_desc, CUBLASLT_MATMUL_DESC_EPILOGUE, &epilogue, sizeof(epilogue)));
  float* bias_ptr = bias_eff.data_ptr<float>();
  CUBLASLT_CHECK(cublasLtMatmulDescSetAttribute(
      op_desc, CUBLASLT_MATMUL_DESC_BIAS_POINTER, &bias_ptr, sizeof(bias_ptr)));

  cublasLtMatrixLayout_t a_desc = nullptr, b_desc = nullptr, c_desc = nullptr;
  CUBLASLT_CHECK(cublasLtMatrixLayoutCreate(&a_desc, CUDA_R_32F, K, N, K));
  CUBLASLT_CHECK(cublasLtMatrixLayoutCreate(&b_desc, CUDA_R_32F, K, M, K));
  CUBLASLT_CHECK(cublasLtMatrixLayoutCreate(&c_desc, CUDA_R_32F, N, M, N));

  const float alpha = (float)mul;
  const float beta = 0.0f;

  typedef std::tuple<int64_t, int64_t, int64_t, int> Key;
  static std::map<Key, cublasLtMatmulHeuristicResult_t> algo_cache;
  const Key key = std::make_tuple(M, N, K, use_tf32);

  cublasLtMatmulHeuristicResult_t heuristic;
  std::map<Key, cublasLtMatmulHeuristicResult_t>::iterator it =
      algo_cache.find(key);
  if (it != algo_cache.end()) {
    heuristic = it->second;
  } else {
    cublasLtMatmulPreference_t pref = nullptr;
    CUBLASLT_CHECK(cublasLtMatmulPreferenceCreate(&pref));
    size_t max_workspace = 64ull * 1024ull * 1024ull;
    CUBLASLT_CHECK(cublasLtMatmulPreferenceSetAttribute(
        pref, CUBLASLT_MATMUL_PREF_MAX_WORKSPACE_BYTES, &max_workspace,
        sizeof(max_workspace)));

    const int max_results = 8;
    cublasLtMatmulHeuristicResult_t results[8];
    int returned = 0;
    CUBLASLT_CHECK(cublasLtMatmulAlgoGetHeuristic(
        getLtHandle(), op_desc, a_desc, b_desc, c_desc, c_desc, pref,
        max_results, results, &returned));
    cublasLtMatmulPreferenceDestroy(pref);
    TORCH_CHECK(returned > 0, "cublasLt found no suitable algorithm");

    size_t ws = 1;
    for (int i = 0; i < returned; ++i) {
      if (results[i].workspaceSize > ws) {
        ws = results[i].workspaceSize;
      }
    }
    auto workspace = at::empty({(int64_t)ws}, xc.options().dtype(at::kByte));

    // One-time micro autotune over the candidate algorithms.
    cudaEvent_t ev0, ev1;
    cudaEventCreate(&ev0);
    cudaEventCreate(&ev1);
    float best_ms = 1e30f;
    int best = -1;
    for (int i = 0; i < returned; ++i) {
      cublasStatus_t st = cublasLtMatmul(
          getLtHandle(), op_desc, &alpha,
          wc.data_ptr<float>(), a_desc,
          x2.data_ptr<float>(), b_desc,
          &beta,
          out.data_ptr<float>(), c_desc,
          out.data_ptr<float>(), c_desc,
          &results[i].algo, workspace.data_ptr(), results[i].workspaceSize,
          stream);
      if (st != CUBLAS_STATUS_SUCCESS) {
        continue;
      }
      cudaEventRecord(ev0, stream);
      for (int r = 0; r < 5; ++r) {
        cublasLtMatmul(getLtHandle(), op_desc, &alpha,
                       wc.data_ptr<float>(), a_desc,
                       x2.data_ptr<float>(), b_desc,
                       &beta,
                       out.data_ptr<float>(), c_desc,
                       out.data_ptr<float>(), c_desc,
                       &results[i].algo, workspace.data_ptr(),
                       results[i].workspaceSize, stream);
      }
      cudaEventRecord(ev1, stream);
      cudaEventSynchronize(ev1);
      float ms = 0.0f;
      cudaEventElapsedTime(&ms, ev0, ev1);
      if (ms < best_ms) {
        best_ms = ms;
        best = i;
      }
    }
    cudaEventDestroy(ev0);
    cudaEventDestroy(ev1);
    TORCH_CHECK(best >= 0, "no runnable cublasLt algorithm found");
    heuristic = results[best];
    algo_cache.emplace(key, heuristic);
  }

  const size_t ws_bytes =
      heuristic.workspaceSize > 0 ? heuristic.workspaceSize : (size_t)1;
  auto workspace =
      at::empty({(int64_t)ws_bytes}, xc.options().dtype(at::kByte));

  CUBLASLT_CHECK(cublasLtMatmul(
      getLtHandle(), op_desc, &alpha,
      wc.data_ptr<float>(), a_desc,
      x2.data_ptr<float>(), b_desc,
      &beta,
      out.data_ptr<float>(), c_desc,
      out.data_ptr<float>(), c_desc,
      &heuristic.algo,
      workspace.data_ptr(), heuristic.workspaceSize,
      stream));

  cublasLtMatrixLayoutDestroy(a_desc);
  cublasLtMatrixLayoutDestroy(b_desc);
  cublasLtMatrixLayoutDestroy(c_desc);
  cublasLtMatmulDescDestroy(op_desc);

  return out.reshape(out_sizes);
}

torch::Tensor sub_mul_relu(torch::Tensor y, double sub, double mul) {
  TORCH_CHECK(y.is_cuda(), "CUDA tensor required");
  TORCH_CHECK(y.scalar_type() == at::kFloat, "FP32 tensor required");
  auto yc = y.contiguous();
  auto out = at::empty_like(yc);
  const long n = (long)yc.numel();
  if (n == 0) {
    return out;
  }
  cudaStream_t stream = at::cuda::getCurrentCUDAStream();
  const float* in_ptr = yc.data_ptr<float>();
  float* out_ptr = out.data_ptr<float>();
  const int threads = 256;
  if ((n & 3) == 0) {
    const long n4 = n >> 2;
    long blocks = (n4 + threads - 1) / threads;
    if (blocks > 16384) blocks = 16384;
    sub_mul_relu_vec4_kernel<<<(int)blocks, threads, 0, stream>>>(
        reinterpret_cast<const float4*>(in_ptr),
        reinterpret_cast<float4*>(out_ptr), n4, (float)sub, (float)mul);
  } else {
    long blocks = (n + threads - 1) / threads;
    if (blocks > 65536) blocks = 65536;
    sub_mul_relu_kernel<<<(int)blocks, threads, 0, stream>>>(
        in_ptr, out_ptr, n, (float)sub, (float)mul);
  }
  return out;
}
"""

_ext = load_inline(
    name="fused_linear_sub_mul_relu_v3",
    cpp_sources=_cpp_src,
    cuda_sources=_cuda_src,
    functions=["linear_sub_mul_relu", "sub_mul_relu"],
    verbose=False,
    extra_cflags=["-O3"],
    extra_cuda_cflags=["-O3"],
    extra_ldflags=["-lcublas", "-lcublasLt"],
)


class ModelNew(nn.Module):
    """
    Optimized version of Model.

    The whole forward (matmul + bias + subtract + multiply + ReLU) is fused
    into a single custom cublasLt-based CUDA operator by folding the subtract
    into the bias vector and the multiply into the GEMM alpha, using a TF32
    tensor-core GEMM (explicitly allowed) with a fused ReLU+bias epilogue and
    a one-time algorithm autotune. If the fused path is unavailable, it falls
    back to cuBLAS linear followed by a custom fused subtract-multiply-ReLU
    kernel.
    """

    def __init__(self, in_features, out_features, subtract_value,
                 multiply_value):
        super(ModelNew, self).__init__()
        self.linear = nn.Linear(in_features, out_features)
        self.subtract_value = float(subtract_value)
        self.multiply_value = float(multiply_value)
        self._use_fused = True
        # TF32 tensor-core math is explicitly permitted for this task; make
        # sure the ATen fallback path also benefits from it.
        if torch.cuda.is_available():
            try:
                torch.backends.cuda.matmul.allow_tf32 = True
            except Exception:
                pass

    def forward(self, x):
        if x.is_cuda and x.dtype == torch.float32:
            weight = self.linear.weight
            bias = self.linear.bias
            if self._use_fused and bias is not None:
                try:
                    return _ext.linear_sub_mul_relu(
                        x, weight, bias, self.subtract_value,
                        self.multiply_value)
                except RuntimeError:
                    self._use_fused = False
            y = F.linear(x, weight, bias)
            return _ext.sub_mul_relu(y, self.subtract_value,
                                     self.multiply_value)
        # CPU fallback: reference computation.
        x = self.linear(x)
        x = x - self.subtract_value
        x = x * self.multiply_value
        return torch.relu(x)
```

Write an improved complete ModelNew: fix any error, and if the solution is already correct, make it faster. Output the new code in one ```python codeblock. Just the model code, no other text, and NO testing code.


Precision rule: the timed forward must compute in FP32 (TF32 tensor-core math is allowed, as in the PyTorch reference). Do not cast inputs, weights or intermediate results to float16 or bfloat16 and do not call half-precision kernels in forward().
