T2= 1 win1  pat allidle 1.83e-05 vs sim.py 1.07e-05: allidle/sim.py 1.71 [1.24, 2.36]
T2= 1 win1  fm  allidle 2.99e-05 vs sim.py 2.65e-05: allidle/sim.py 1.13 [0.81, 1.57]
T2= 1 win1  gain pattern/free allidle 0.61 [0.40, 0.94] vs sim.py pooled 0.40 [0.34, 0.48]
T2= 1 cyc1  pat allidle 2.32e-05 vs sim.py 1.07e-05: allidle/sim.py 2.17 [1.58, 2.97]
T2= 1 cyc1  fm  allidle 6.27e-05 vs sim.py 2.65e-05: allidle/sim.py 2.37 [1.72, 3.26]
T2= 1 cyc1  gain pattern/free allidle 0.37 [0.24, 0.56] vs sim.py pooled 0.40 [0.34, 0.48]
T2= 3 win3  pat allidle 1.35e-06 vs sim.py 1.17e-06: allidle/sim.py 1.15 [0.84, 1.57]
T2= 3 win3  fm  allidle 7.77e-07 vs sim.py 5.83e-07: allidle/sim.py 1.33 [0.98, 1.82]
T2= 3 win3  gain pattern/free allidle 1.74 [1.24, 2.43] vs sim.py pooled 2.01 [1.51, 2.68]
T2=10 win10 pat allidle 3.49e-07 vs sim.py 3.11e-07: allidle/sim.py 1.12 [0.86, 1.46]
T2=10 win10 fm  allidle 1.1e-07 vs sim.py 9.95e-08: allidle/sim.py 1.11 [0.82, 1.50]
T2=10 win10 gain pattern/free allidle 3.16 [2.22, 4.49] vs sim.py pooled 3.12 [2.59, 3.76]
allidle window crossover (log-log interpolation 1 s -> 3 s, not measured): T2 ~ 1.68 s (model units)
